Texas Instruments TMS320DM335, Руководство пользователя

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6.6.3 PLL Control (PLLCTL)
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PLL Controller Register Map
The PLL control register is shown in Figure 6-5 and described in Table 6-6 for PLLC1 and PLLC2.
Figure 6-5. PLL Control Register (PLLCTL)
31 16
Reserved
R-0
15 9 8 7 6 5 4 3 2 1 0
Reserved CLKMOD PLLSELB Reserved PLLENSR PLLDIS PLLRST Reserved PLLPWRDN PLLEN
E C
R-0 R/W-0 R/W-1 R-0 R/W-1 R/W-1 R/W-1 R-0 R/W-1 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 6-6. PLL Control Register (PLLCTL) Field Descriptions
Bit Field Value Description
31-9 Reserved 0 Reserved
8 CLKMODE Reference Clock Selection. This bit has no effect for PLLC2. In the device, a single oscillator or
CLKIN square wave is input to both PLLC1 and PLLC2.
0 Internal oscillator
1 CLKIN square wave
7 PLLSELB Selects PLL A versus PLL B.
0 PLL A is selected. PLL B is put in power down.(pll_b_pwrdn_po = 1)
1 PLL B is selected. PLL A is put in power down(pll_a_pwrdn_po = 1)
6 Reserved 0 Reserved
5 PLLENSRC PLL enable source. This bit must be cleared to 0 before PLLCTL.PLLEN will have any effect.
0 PLL enable is controlled by the register bit PLLCTL.PLLEN
1 PLL enable is controlled by internal test hardware
4 PLLDIS PLL disable
0 PLL disable de-assert
1 PLL disable assert
3 PLLRST PLL reset
0 PLL reset de-assert
1 PLL reset assert
2 Reserved 0 Reserved
1 PLLPWRDN PLL power-down
0 PLL operating, not powered down
1 PLL power-down
0 PLLEN PLL Mode Enable. Bit PLLCTL.PLLENSRC must be cleared to 0 before PLLCTL.PLLEN will have
any effect.
0 Bypass mode
1 PLL mode, not bypassed
SPRUFX7 – July 2008 PLL Controllers (PLLCs) 47
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