8.4.7 Interrupt Enable Register 0 (EINT0)
INTC Registers
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The interrupt enable register 0 (EINT0) is shown in
and described in
.
Figure 8-11. Interrupt Enable Register 0 (EINT0)
31
0
EINT[31:0]
R/W-0
LEGEND: R/W = Read/Write; n = value at reset
Table 8-9. Interrupt Enable Register 0 (EINT0) Field Descriptions
Bit
Field
Value
Description
31-0
EINT[31:0]
Interrupt enable for INTx.
0
Mask interrupt
1
Enable interrupt
Interrupt Controller
100
SPRUFX7 – July 2008