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8-12
Interrupt Enable Register 1 (EINT1)
....................................................................................
8-13
Interrupt Operation Control Register (INTCTL)
.......................................................................
8-14
EABASE
8-15
Interrupt Priority Register 0 (INTPRI0)
.................................................................................
8-16
Interrupt Priority Register 1 (INTPRI1)
.................................................................................
8-17
Interrupt Priority Register 2 (INTPRI2)
.................................................................................
8-18
Interrupt Priority Register 3 (INTPRI3)
.................................................................................
8-19
Interrupt Priority Register 4 (INTPRI4)
.................................................................................
8-20
Interrupt Priority Register 5 (INTPRI5)
.................................................................................
8-21
Interrupt Priority Register 6 (INTPRI6)
.................................................................................
8-22
Interrupt Priority Register 7 (INTPRI7)
.................................................................................
9-1
PINMUX0 - Pin Mux 0 (Video In) Pin Mux Register
..................................................................
9-2
PINMUX1 - Pin Mux 1 (Video Out) Pin Mux Register
................................................................
9-3
PINMUX2 - Pin Mux 2 (AEMIF) Pin Mux Register
...................................................................
9-4
PINMUX3 - Pin Mux 3 (GIO/Misc) Pin Mux Register
................................................................
9-5
PINMUX4 - Pin Mux 4 (Misc) Pin Mux Register
......................................................................
9-6
BOOTCFG - Boot Configuration
........................................................................................
9-7
ARM_INTMUX - ARM Interrupt Mux Control Register
...............................................................
9-8
EDMA_EVTMUX - EDMA Event Mux Control Register
.............................................................
9-9
DDR_SLEW - DDR Slew
................................................................................................
9-10
CLKOUT - CLKOUT div/out Control
....................................................................................
9-11
DEVICE_ID - Device ID
..................................................................................................
9-12
VDAC_CONFIG - Video Dac Configuration
...........................................................................
9-13
TIMER64_CTL - Input Control
.............................................................................
9-14
USB_PHY_CTRL - USB PHY Control
................................................................................
9-15
MISC - Miscellaneous Control
..........................................................................................
9-16
MSTPRI0 - Master Priorities 0
..........................................................................................
9-17
Master Priorities 1(MSTPRI1) Register
................................................................................
9-18
VPSS_CLK_CTRL - VPSS Clock Mux Control
......................................................................
9-19
Deep Sleep Mode Configuration (DEEPSLEEP) Register
..........................................................
9-20
DEBOUNCE[8] - De-bounce for GIO[n] Input
.........................................................................
9-21
VTP IO Control Register (VTPIOCR)
..................................................................................
11-1
Boot Modes Overview
....................................................................................................
11-2
Boot Mode Functional Block Diagram
.................................................................................
11-3
NAND Boot Flow
11-4
4-Bit ECC Format and Bit 10 to 8-Bit Compression Algorithm
.....................................................
11-5
4-Bit ECC Format for 2048+64 Byte Page Size
......................................................................
11-6
NAND Boot Mode Flow Chart
...........................................................................................
11-7
ARM NAND ROM Boot Loader Example
..............................................................................
11-8
Descriptor Search for ARM NAND Boot Mode
.......................................................................
11-9
MMC/SD Boot Mode Overview
.........................................................................................
11-10 MMC/SD Boot Mode Flow Chart
.......................................................................................
11-11 ARM MMC/SD ROM Boot Loader Example
...........................................................................
11-12 Descriptor Search for ARM MMC/SD Boot Mode
....................................................................
11-13 UART Boot Mode Handshake
...........................................................................................
11-14 Host Utility Timing
SPRUFX7 – July 2008
List of Figures
9