8.3
INTC Methodology
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INTC Methodology
Table 8-1. AINTC Interrupt Connections (continued)
Interrupt
Acronym
Source
Interrupt
Acronym
Source
Number
Number
5
VPSSINT5
VPSS - INT5
37
PWMINT1
PWM 1
6
VPSSINT6
VPSS - INT6
38
PWMINT2
PWM2
7
VPSSINT7
VPSS - INT7
39
I2CINT
I2C
8
VPSSINT8
VPSS - INT8
40
UARTINT0
UART0
9
Reserved
41
UARTINT1
UART1
10
Reserved
42
SPINT0-0
SPI0
11
Reserved
43
SPINT0-1
SPI0
12
USBINT
USB OTG Collector
44
GPIO0
GPIO
13
RTOINT or
RTO or
45
GPIO1
GPIO
TINT4
Timer 2 - TINT12
SYS.ARM_INTMUX
14
UARTINT2 or
UART2 or
46
GPIO2
GPIO
TINT5
Timer 2 - TINT34
15
TINT6
Timer 3 TINT12
47
GPIO3
GPIO
16
CCINT0
EDMA CC Region 0
48
GPIO4
GPIO
17
SPINT1-0 or
SPI1 or
49
GPIO5
GPIO
CCERRINT
EDMA CC Error
18
SPINT1-1 or
SPI1 or
50
GPIO6
GPIO
TCERRINT0
EDMA TC0 Error
19
SPINT2-0 or
SPI2 or
51
GPIO7
GPIO
TCERRINT1
EDMA TC1 Error
20
PSCINT
PSC - ALLINT
52
GPIO8
GPIO
21
SPINT2-1
SPI2
53
GPIO9
GPIO
22
TINT7
Timer3 - TINT34
54
GPIOBNK0
GPIO
23
SDIOINT0
MMC/SD0
55
GPIOBNK1
GPIO
24
MBXINT0 or
ASP0 or
56
GPIOBNK2
GPIO
MBXINT1
ASP1
25
MBRINT0 or
ASP0 or
57
GPIOBNK3
GPIO
MBRINT1
ASP1
26
MMCINT0
MMC/SD0
58
GPIOBNK4
GPIO
27
MMCINT1
MMC/SC1
59
GPIOBNK5
GPIO
28
PWMINT3
PWM3
60
GPIOBNK6
GPIO
29
DDRINT
DDR EMIF
61
COMMTX
ARMSS
30
AEMIFINT
Async EMIF
62
COMMRX
ARMSS
31
SDIOINT1
SDIO1
63
EMUINT
E2ICE
INTC methodology is illustrated in
and described below.
•
When an interrupt occurs, the status is reflected in either the FIQn or the IRQn registers, depending
upon the interrupt type selected.
•
Interrupts are enabled or disabled (masked) by setting the EINTn register.
Note:
Even if an interrupt is masked, the status interrupt is still reflected in the FIQn and the IRQn
registers.
•
When an interrupt from any interrupt channel occurs (for which interrupt is enabled), an IRQ or FIQ
interrupt generates to the ARM926 core (depending on whether the interrupt channel is mapped to IRQ
or FIQ interrupt). The ARM then branches to the IRQ or FIQ interrupt routine.
SPRUFX7 – July 2008
Interrupt Controller
89