Texas Instruments TMS320DM335, Руководство пользователя

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6.5.2.2 Pre-Divider (PREDIV), PLL Multiplier (PLLM), and Post-Divider (POSTDIV)
6.5.3 PLL Power Down and Wakeup
6.6 PLL Controller Register Map
6.6.1 Introduction
PLL Controller Register Map
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To change the values of PREDIV, PLLM, or POSTDIV; the PLL controller must first be placed in bypass
mode. Perform the following steps to modify PREDIV, PLLM, or POSTDIV ratios.
1. In PLLCTL, write PLLEN = 0 to place the PLL in bypass mode.
2. Wait at least 4 reference clock cycles for the PLLEN mux to change.
3. In PLLCTL, write PLLRST = 1 (assert PLL).
4. Modify PREDIV, PLLM, and/or POSTDIV ratios.
5. Wait at least 5 miro-seconds for the PLL reset.
6. In PLLCTL, write PLLRST = 0 (de-assert PLL reset)
7. Wait at least 8000 reference clock cycles for the PLL to lock.
8. In PLLCTL, write PLLEN = 1 (switch from bypass mode to PLL mode).
The PLL may be powered down, in which case the PLL controller is in bypass mode and the device runs
from input reference clock. The device is still able to run when the PLL is powered down because it is still
being clocked by the bypass clock.
Perform the following procedure to power down the PLL.
1. In PLLCTL, write PLLEN = 0 (bypass mode).
2. Wait at least 4 reference clock cycles for the PLLEN mux to change.
3. In PLLCTL, write PLLPWRDN = 1 to power down the PLL.
To wakeup the PLL from its power-down mode, follow the PLL sequence described in Section 6.5.1.1 .
Table 6-3 lists the base address for the PLLC1 and PLLC2 registers. Table 6-4 lists the memory-mapped
registers for PLLC1 and PLLC2. Also, see the device memory map Table 4-2 for the base addresses of
these registers.
Table 6-3. PLL and Reset Controller Module Instance Table
Instance ID Base Address End Address Size
PLLC1 0x1C4 0800 0x1C4 0BFF 0x 400
PLLC2 0x1C4 0C00 0x1C4 0FFF 0x 400
Table 6-4. PLLC Registers
Offset Acronym Register Description Section
00h PID Contains peripheral ID and revision information Section 6.6.2
100h PLLCTL Controls PLL operations Section 6.6.3
110h PLLM PLL Multiplier Control Section 6.6.4
114h PREDIV Pre-divider control Section 6.6.5
118h PLLDIV1 Divider 1 control-divider for SYSCLK1 Section 6.6.6
11Ch PLLDIV2 Divider 2 control-divider for SYSCLK2 Section 6.6.7
120h PLLDIV3 Divider 3 control-divider for SYSCLK3 Section 6.6.8
128h POSTDIV Post-divider control Section 6.6.9
12Ch BPDIV Bypass divider control Section 6.6.10
44 PLL Controllers (PLLCs) SPRUFX7 – July 2008
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