9.10.4 PINMUX2 - Pin Mux 2 (AEMIF) Pin Mux Register
System Control Register Descriptions
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The PINMUX2 register controls pin multiplexing for the AEMIF pins. Some of the register fields have
default values set by external pins that allow control of the AEMIF configuration to match the boot mode.
Figure 9-3. PINMUX2 - Pin Mux 2 (AEMIF) Pin Mux Register
31
24
Reserved
R-0
23
16
Reserved
R-0
15
12
11
10
9
8
Reserved
EM_CLK
EM_ADV
EM_WAIT
EM_WE_OE
R-0
R/W-0
R/W-1
R/W-0
R/W-0
7
6
5
4
3
2
1
0
EM_CE1
EM_CE0
EM_D7_0
EM_D15_8
EM_BA0
EM_A0_BA1
EM_A13_3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 9-6. PINMUX2 - Pin Mux 2 (AEMIF) Pin Mux Register Field Descriptions
Bit
Field
Value
Description
31-12
Reserved
0
Reserved Must be set to 0.
11
EM_CLK
Enable EM_CLK (AEMIF Pin Mux)
0
EM_CLK
1
GIO[31]
10
EM_ADV
Enable EM_ADV (AEMIF Pin Mux)
0
EM_ADV - Address Valid Detect for OneNAND
1
GIO[32]
9
EM_WAIT
Enable EM_WAIT (AEMIF Pin Mux)
0
EM_WAIT
1
GIO[33]
8
EM_WE_OE
Enable EM_WE_OE (AEMIF Pin Mux)
0
EM_WE & EM_OE
1
GIO[35:34]
7
EM_CE1
Enable EM_CE1 (AEMIF Pin Mux)
0
EM_AO
1
GIO[36]
6
EM_CEO
Enable EM_CE0 (AEMIF Pin Mux)
0
EM_CE0
1
GIO[37]
5
EM_D7_0
Enable EM_D[7:0] (AEMIF Pin Mux)
0
EM_D[7:0]
1
GIO[45:38]
122
System Control Module
SPRUFX7 – July 2008