9.10.6 PINMUX4 - Pin Mux 4 (Misc) Pin Mux Register
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System Control Register Descriptions
The PINMUX4 register controls pin multiplexing for SPI0 and MMC/SD0.
Figure 9-5. PINMUX4 - Pin Mux 4 (Misc) Pin Mux Register
31
3
2
1
0
Reserved
MMCSD0_MS
SPI0_SDI
SPI0_SDENA
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write, R = Read only; n = value at reset
Table 9-8. PINMUX4 - Pin Mux 4 (Misc) Pin Mux Register Field Descriptions
Bit
Field
Value
Description
31-3
Reserved
0
Reserved
2
MMCSD0_MS
Enable MMCSD0_MS
0
MMC/SD[0] - SD0_CLK,SD0_CMD & SD0_DATA[3:0]
1
Reserved
1
SPI0_SDI
Enable SPI0_SDI
0
SPI0_SDI
1
GIO[32]
0
SPI0_SDENA
Enable SPI0_SDENA0
0
SPI0_SDENA[0]
1
GIO[103]
SPRUFX7 – July 2008
System Control Module
127