MAX 10 NEEK
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www.terasic.com
February 4, 2016
Chapter 4
NEEK10 System Builder
This chapter introduces the NEEK 10 System Builder to help users get started in creating their own
projects in literally minutes. It also describes the design flow and includes an example for users to
get familiar with the tool.
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The NEEK10 System Builder is a Windows-based utility. It is created to help users build a top
project for NEEK10 within minutes. The generated Quartus II project files include:
Quartus II project file (.qpf)
Quartus II setting file (.qsf)
Top-level design file (.v)
Synopsis design constraints file (.sdc)
Pin assignment document (.htm)
The above files generated by the NEEK10 System Builder can also prevent situations that are prone
to compilation error when users manually edit the top-level design file or place pin assignment. The
common mistakes that users encounter are:
Board is damaged due to incorrect bank voltage setting or pin assignment.
Board is malfunctioned because of wrong device chosen, declaration of pin location, or the
direction is incorrect/forgotten.
Performance degradation due to improper pin assignment.
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The design flow of building a Quartus II project for NEEK10 using the NEEK10 System Builder is
illustrated in
Figure 4-1
. It gives users an overview about the steps, starting from launching the
System Builder to configuring the FPGA. The left-hand side of the chart can be done within
minutes. After users enter the design requirements, the NEEK10 System Builder will generate
Quartus II project files, Quartus II setting file, top-level design file, Synopsis design constraint file,
and the pin assignment document.
The top-level design file contains a top-level Verilog HDL wrapper for users to add their own
