MAX 10 NEEK
51
www.terasic.com
February 4, 2016
Data Transmission from the Controller to Device
When the PS/2 controller wants to transmit data to device, it first pulls the clock line low for more
than one clock cycle to inhibit the current transmission process or to indicate the start of a new
transmission process, which is usually called as inhibit state. It then pulls low the data line before
releasing the clock line. This is called the request state. The rising edge on the clock line formed by
the release action can also be used to indicate the sample time point as for a start bit. The device
will detect this succession and generates a clock sequence in less than 10ms time. The transmit data
consists of 12bits, one start bit (as explained before), eight data bits, one parity check bit (odd
check), one stop bit (always one), and one acknowledge bit (always zero).
After sending out the parity check bit, the controller should release the data line, and the device will
detect any state change on the data line in the next clock cycle. If there’s no change on the data line
for one clock cycle, the device will pull low the data line again as an acknowledgement which
means that the data is correctly received.
After the power-on cycle of the PS/2 mouse, it enters into stream mode automatically and disable
data transmit unless an enabling instruction is received.
Figure 5-1
shows the waveform while
communication happening on two lines.
Figure 5-1 Waveform of Clock and Data Signals during Data Transmission
