MAX 10 NEEK
17
www.terasic.com
February 4, 2016
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Figure 3-10
shows the default frequency of all external clocks to the MAX 10 FPGA. A clock
generator is used to distribute clock signals with low jitter. The three 50MHz clock signals
connected to the FPGA are used as clock sources for user logic. One 25MHz clock signal is
connected to the clock input of Gigabit Ethernet Transceiver. One 24MHz clock signal is connected
to the clock inputs of USB microcontroller of USB Blaster II. One 28.63636MHz clock signal is
connected to the clock input of HDMI Receiver chip. The other 50MHz clock signal is connected to
MAX CPLD of USB Blaster II. One 10MHz clock signal is connected to the PLL1 and PLL3 of
FPGA, the outputs of these two PLLs can drive ADC clock. The associated pin assignment for
clock inputs to FPGA I/O pins is listed in
Table 3-2.
Figure 3-10 Block diagram of the clock distribution on MAX 10 NEEK
