MAX 10 NEEK
106
www.terasic.com
February 4, 2016
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This section describes some details about the design of the application selector utility.
Figure 7-2 Block Diagram Of Application Selector
Figure 7-2
shows the hardware block diagram of this demonstration. The system requires a 50 MHz
clock provided from the board. The PLL generates a 100MHz clock for Nios II processor and the
other controllers. The DDR3 works as the system memory. The Nios II processor writes the display
content to the DDR3. The SG-DMA reads the data and translates it to the VGA controller through
the Avalon Streaming interface. The I2C controller and the PIO Controller are implemented to get
the touch action data of the MTL2 touch screen.
The Nios II processor accesses the SD card through an SD card SPI controller. The Application
Selector uses an SD card for storing applications hardware and software binary files. The SD card
must be formatted with the FAT16/32 file system. Long file names are supported.
The Dual Configuration IP provides an Avalon-MM interface for NIOS II processor to access the
remote system upgrade circuitry in the MAX10 FPGA device. It’s the critical part of this
demonstration. The Altera Dual Configuration IP core offers the following capabilities through
