Telecommunications Techniques Corporation interceptor 147, Справочное руководство, Страница: 254 / 280

Remote Control Status Registers
C-10
C
INTERCEPTOR 147 2 Mbit/s and Data Analyzer
The Line Status Register gives the current state of the
signal presence indicator, the various FAS Sync indicators,
the pattern slip indicator, and an alarm indicator. The Line
Status Register is read with the query, STATUS:LINE?.
The bit grouping is as follows:
Bit 7 Not used. Always set to 0.
Bit 6 Not used. Always set to 0.
Bit 5 CRC
Set to 1 when the INTERCEPTOR 147 has
detected CRC framing.
Bit 4 PATTERN INVERT
Set to 1 when the INTERCEPTOR 147 has
detected pattern inversion.
Bit 3 PATTERN SYNC
Set to 1 when the INTERCEPTOR 147 has
detected pattern sync.
Bit 2 MFAS SYNC
Set to 1 when the INTERCEPTOR 147 has
detected MFAS Sync.
Bit 1 FAS SYNC
Set to 1 when the INTERCEPTOR 147 has
detected FAS Sync.
Bit 0 SIGNAL PRESENT
Set to 1 when the INTERCEPTOR 147
detects that an input signal is present.
The Line History Register provides the history of the
signal presence indicator, various FAS Sync indicators,
pattern slip indicator, and the alarm indicators since the
Line History Register was last read. A set bit generally
indicates an error has occurred or synchronization was lost
during the interval since the register was last read.