Telecommunications Techniques Corporation interceptor 147, Справочное руководство, Страница: 138 / 280

Remote Control
6-10
6
INTERCEPTOR 147 2 Mbit/s and Data Analyzer
The bits of the Parallel Poll Enable Register include:
Bit 0 Error Available
Bit 1 0
Bit 2 Test Status Summary
Bit 3 0
Bit 4 0
Bit 5 Event Status Summary
Bit 6 Master Status Summary
Bit 7 0
*PSC [<int> | ?]
Power-on Status Clear command/query
Use the *PSC command to set the power-on status clear bit
setting of the INTERCEPTOR 147, using the following
values for <int>.
1 The INTERCEPTOR 147 automatically clears
all of the Status Enable Registers when powered
on. This setting prevents the INTERCEPTOR
147 from generating a service request when it is
powered on.
0 The INTERCEPTOR 147 does not clear the
enable registers when powered ON.
The *PSC? query requests the current power-on status
clear setting.
Example:
>*
PSC 0
Preserves the Status Enable Registers
through a power cycle.
>*
PSC?
Requests the current value of the power-
on status clear setting.
0
*RCL <int>
Recall Stored Test Setups command only
The *RCL command causes the INTERCEPTOR 147 to
recall a stored test setup. This command is the same as the
Program Recall item in the AUXILIARY category. Unlike
the Program Recall item, however, the remote control and