Stanford Research Systems SR620, Руководство пользователя

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Circuit Description 83
SR620 Universal Time Interval Counter
There are three basic modes for external arming:
EXT ±Time, EXT +Time, and EXT +Time with
Stop Holdoff. In addition, each of these modes
may be used with delayed and scanning gates.
The arming criteria which applied in +Time and
±Time also apply in EXTernal arming, except that
the Start_En and Stop_En are not set when the
Load line goes low. If positive logic is selected for
the EXT input, and the EXT +Time with Stop
Holdoff is selected, then the rising edges of the
EXT input will set Start-En, and the falling edge of
the EXT input will set Stop-En. Note that stop
pulses are inhibited until the falling edge of the
EXT input.
If stop holdoff is not selected, then the Par/Hoff
line is low, and the Stop_En flip-flop (U506B) will
be set by U505B when Start_En occurs. In this
case, stop pulses are not held off by the EXTernal
input.
TIME INTEGRATORS
(Sheet 11 of 16)
The time interval resolution of 4 ps is attained by
measuring the duration of the Start_Ck and
Stop_Ck pulses. The descriptions of the two
integrators are identical: circuit references will be
made to the Start_Ck integrator.
The integrating capacitor, C701, integrates a
constant current source for the duration of the
Start_Ck pulse. The change of voltage change on
this capacitor is proportional to the width of the
START_TO_CK pulse.
Before the unit is triggered, U701A, an operational
transconductance amplifier (OTA), precharges the
integrating capacitor to about 7 vdc. When the
Start is asserted, Q702 is turned off, and Q701 is
turned on, turning off the OTA. At the same time,
the constant current source (at the common
emitters of U702A) is switched from N701A to
N701B, to discharge the integrating capacitor at a
constant rate. The discharge is stopped when the
Start_Ck pulse terminates.
The constant current source is maintained by
U703A & B which holds the voltage across R714
constant. The time to voltage gain coefficient is
calibrated by the dc voltage, Start_Gain.
The integrating capacitor's voltage is buffered and
amplified by U703C. The amplified output will
range from +/-3.33 Vdc (with some offset). This
voltage is sampled and held by the analog switch,
U705A, on the polypropylene capacitor, C706. The
analog switch is turned on for about 7 us by the
one-shot, U704A. Another analog switch, U705D
is released just before the signal is sampled: this
switch is used to discharge the capacitor of the
previous sampled signal. U703D buffers the
sampled voltage to the ADC converter. The signal
to the A/D converter covers 2/3 of its 4096 bit
range with a Start_Ck range of 11.11 ns, implying
a resolution of 4 ps/bit. To maintain an accuracy
and jitter commensurate with this resolution it is
necessary for the processor to perform some
empirical linearity corrections to the Start_Ck and
the Stop_Ck voltages.
The 7 us strobe to the sample and hold switch,
and the processor interrupt request, Start_Int, is
generated by U704A, a dual one-shot. The one
shot is triggered by the Start pulse, which is
converted to TTL levels by U707A.
ANALOG TO DIGITAL CONVERTER
(Sheet 12 of 16)
U805 is a 12 bit A/D converter. Each conversion
takes about 100 us. Referenced to the buffer
amplifier's output (U810A), the A/D has a full scale
range of +/-5 V. A conversion is initiated when the
processor writes to the A/D converter. Before
starting a conversion, the processor selects the
source with the 1 of 8 analog multiplexer, U803.
Three latched bits, Adc_Mpx, select the source.
The ADC's voltage reference is 5.00 vdc from
U906, which serves as a voltage reference for the
entire unit. The A/D converter can digitize the
Start_Ck or Stop_Ck voltages, the front panel
threshold pot positions, a selected rear panel
DVM inputs or autolevel circuit voltages.
The isolated BNC's on the rear panel are buffered
by the differential amplifiers, U801C & D. The
output of one of these amplifiers is selected by the
analog multiplexers U802A & B. The selected
signal is buffered by U801B, which also amplifies
the signal by about 10 if the switch U802D is
closed. The analog switch, U802C, samples the
amplified output onto C805. The processor closes
the S/H switch for about 20 us prior to conversion.
Calibration bytes for offset and gain correction for
both channels are stored in ROM and RAM.
AUTOLEVEL CIRCUITS
(Sheet 12 of 16)
There are two autolevel circuits which output a
voltage between the peak and minimum levels
seen at the A and B inputs. The circuit references
will be given for the A input.