Stanford Research Systems SR620, Руководство пользователя

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82 Circuit Description
SR620 Universal Time Interval Counter
100% positive reflection at the high impedance
termination (into the TTL or HC device which
receives the signal.) The reflection is then reverse
terminated into the 82 Ohm resistor and the low
impedance output of the sending device. The
result is a logic signal with very little distortion at
the far end of the line.
FAST TIME INTERVAL LOGIC
(Sheet 10 of 16)
To measure a time interval, the 90 MHz clock is
counted for the interval between a start pulse and
a stop pulse. Each tick of the clock represents
11.111 ns of time interval. To attain a resolution of
4 ps, the times from the start pulse and stop pulse
to subsequent edges of clock are measured with 4
ps resolution. The time interval is then (11.111.. ns
x #clocks) + (Time from Start to clock)- (Time from
Stop to clock).
ECL flip-flops have the unfortunate problem that
the propagation delay from clock to output will be
affected if either the reset or data inputs
arechanged simultaneously with the clock. In order
to meet the stringent accuracy and jitter
specifications for the instrument, it is necessary to
use two stage resynchronization.
A rising edge on the ECL bit Start_Mpx sets the
start latch, U604A, asserting "Start". To avoid the
possibility that the start pulse comes just as the
reset to the start latch is released, the start pulse
to the start latch is delayed; the undelayed start
pulse clocks U604B high, synchronously releasing
the reset to the start latch. In this way, the reset to
the start latch always precedes the clock to the
start latch by about 3 ns.
Once the start latch is set, the next rising edge of
the 90 MHz clock will set U605A, and the second
edge of the clock will set U605B. The signal Start-
Ck is on from the start edge until the second edge
of the 90 MHz after the start signal. This 12-23 ns
wide pulse will be integrated to measure the time
by which the start pulse preceded the 90 MHz
clock edge.
The same scheme is used to generate a Stop bit
and Stop-Ck pulse. A Time_Gate is also
generated: this bit is on for the interval between
the start and the stop, resynchronized to the 90
MHz clock. Time_Gate is used to gate the 90 MHz
clock to a counter to measure the number of 90
MHz clock ticks in the time interval.
The flip-flop, U311B, saves the state of the
synchronized stop bit prior to the last rising edge
of the 90 MHz clock. This will set the bit
"Neg_Time" high when the stop pulse proceeds
the start pulse.
TIME INTERVAL ARMING
(Sheets 9 and 10 of 16)
There are several different ways that the start and
stop circuits may be armed. In each case, the
circuits are armed by removing the reset and by
providing a high ECL level to the D inputs of the
start and stop latches. The level at the D inputs is
always high, except in the ±Time arming mode.
The reset is set whenever the "Load" is asserted
by the processor: the reset may be extended
beyond the end of "Load" in several ways.
For +Time and ±Time arming (internal arming), -
Int_Arm is set low. This will cause U506A
(Start_En) to be set when the Load line goes low
(at the end of the reload cycle for the previous
measurement) removing the reset from the latch
(U604B) which is holding the start latch (U604A) in
reset. U506B (Stop_En) is also set high when the
load line goes low, and so the line "Start_En"is set.
In the +Time mode, -P_Time is low, and so the
reset to U608B (which holds the stop latch in
reset) will not be removed until the start latch goes
high: in this way the stop latch is armed by the
start pulse. The Stop_Mpx output is delayed by 15
ns of coax cable, to allow time for the stop latch's
reset to be removed. This allows time intervals
from -1ns to +1000 s to be measured.
For ±TIME mode arming, the "Load" pulse is
extended if a start or stop pulse was not
accompanied by a stop or start pulse while the unit
was converting or reloading. In this mode, -
P/M_Time is low, removing the reset from the
latches U612A&B. The flip-flop U610A is a one bit
counter of start pulses: the U610B is a one bit
counter of stop pulses. The output of the XOR
gates, U611A&C will be high if a start was not
accompanied by a stop. (The output of U611A is
delayed by a few nanoseconds to handle the case
that starts and stops are coincident.) The bit
"Par/Hoff" is used to select the parity of the one-bit
counters which will clock U612A&B to release the
LOAD pulse. If either U612A or B is clocked low,
their wire-or'ed -Q output will set the D input to the
start and stop latches high. Changing the Par/Hoff
bit will allow the compliment period to be
measured. U612A&B are preset by the "Load"
pulse.