Stanford Research Systems SR620, Руководство пользователя

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80 Circuit Description
SR620 Universal Time Interval Counter
The three inputs are nearly identical: reference
designations for channel A will be used in the
description that follows.
The inputs are terminated to 50 Ohms by the
processor activating relay U401. Both poles of the
DPDT relay are used to reduce inductance. The
50 Ohm terminator is a 1/2 watt resistor, so the
average voltage should not exceed 5 Vdc. U407
detects the voltage at the input; if it exceeds - 5
Vdc, or if the RF (buffered by the emitter follower
Q404 and detected by D403) e5 Vdc,
then the -OVLD_A bit is asserted. This bit is polled
by the processor, which opens relay if an overload
is detected. The firmware will then blink the 50
Ohm LED to inform the user that the termination
has been removed.
When the input is terminated into 50 Ohms, the
input signal is ac coupled to the prescaler, U403.
The prescaler has a 10 mV rms sensitivity and can
provide a divide-by-64 output for inputs up to 1.3
GHz. The input to the prescaler is limited to the
bias currents in Q404 and D402. Large positive
excursions will reverse bias D402, and large
negative excursions will turn off Q404. The
prescaler is powered by Q405 if -Pre_A_En is low.
This prevents outputs from the prescaler from
interfering in measurements when it is not needed.
The output from the prescaler is shifted to ECL
levels by the emitter follower on its output.
The input signal is attenuated by R403 and R404,
and compensated by C402. C402 is adjusted for
good pulse response by viewing a step input at the
emitter of Q403 on 10 us/div. The attenuated input
signal is limited by D404,405 and buffered by
Q401, a fast n-channel JFET, and by the emitter
follower Q403. The op amp, U404 adjusts the
drain current in Q401 so as to maintain dc
accuracy across the Q401/Q403 pair.
The buffered outputs of A and B are normally sent
to comparators U408 and U418 respectively by
the relays U405 and U415. The relays are
configured so as to reduce crosstalk between the
A & B inputs. In the case of rise and fall-time
measurements, one input signal is sent to both
comparators, which are set for the low and high
voltage levels for the transition being measured.
The comparator U408 is operated in a Schmitt
trigger configuration with about 20 mV of
hysteresis. Since the input signal has been
attenuated by 2x, this represents 40 mV of
hysteresis at the input. The comparator threshold
is set by the output of U406A which serves as a sample and hold amplifier for C409. The
comparator provides inverted and non-inverted
outputs to the ECL multiplexers on sheet 9 of 16.
The multiplexers chooses one or the other to
trigger on rising or falling edges of the input signal.
TRIGGER MULTIPLEXERS
(Sheet 9 of 16)
Nine bits (FREQx,STARTx and STOPx) from the
processor control the signal source to be used in
time interval and frequency measurements. For
time interval measurements, U502 and U503 can
select either the A or B inputs ( either polarity ) to
form either the start or stop signal. The 1.000KHz
CAL signal may also be selected. U501 can select
from the same signals for frequency
measurements. If a frequency measurement is to
be done, U502 and U503 will select Freq_Start
and Freq_Stop from the frequency gating logic as
the start and stop signals.
FREQUENCY GATES
(Sheet 9 of 16)
The frequency gating circuitry is used to generate
a start and a stop pulse for time interval
measurement. The start pulse (Freq_Start) occurs
on the second transition of the selected source
after the frequency sampling gate is opened; the
stop pulse (Freq_Stop) occurs on the second
transition of the selected frequency source after
the frequency gate is closed. The circuit also
generates Freq_Gate so that the number of cycles
may be counted. Dividing the number of cycles by
the time interval gives the frequency.
If the signal -Fast_Per is asserted, then the Start
pulse occurs on the FIRST transition of the
selected source after the frequency sampling gate
is opened; the stop pulse occurs on the FIRST
transition of the selected frequency source after
the frequency gate is closed. This allows the time
between a single event pair to be measured. This
mode is not used.
There are four modes of gating: a fixed gate of 1
us to 1s duration, gates which may be delayed or
scanned relative to and external trigger, an
external gate of arbitrary duration, or gating to time
a single period of the input waveform.
For internally generated gates the bit Int_Gaten is
set high, and the gate is controlled by the bit
Gate_Ctrl. The Gate_Ctrl bit may provide fixed
gates or gates which are delayed or scanned
relative to and external trigger. The rising edge of