Circuit Description
79
SR620 Universal Time Interval Counter
front panel EXT input. The control signals
Sel_Cmp3 and Sel_-Cmp3 are used to select the
rising or falling edge of the EXT input to start the
delay. U244A will be clocked high by -Cmp_3
going low if Sel_Cmp3 is set high, and U244B will
be clocked high by -Cmp_3 going high if Sel_-
Cmp3 is set high.
For delayed gates, the programming of the 8254's
is quite different. In this case, the period of the
output of the 2/3 of the 8254 is set to the gate
width, and the 3/3 of the 8254 is programmed to
go low for one clock cycle after counting down the
delay. Of course, the programmed delay must be
some integer number of gate widths. The firmware
supports gate widths (and delay resolution) from 1
us to 10 ms in a 1-2-5 sequence.
TIMEBASE
(Sheet 7 of 16)
The standard timebase is U1A, a 10.00000 MHz, 1
ppm, TCXO with aging characteristics of about 1
ppm/yr. U1A is powered by U301 which re-
reg15 VDC to +5 VDC. U1A provides a 10
MHz sine output.
The optional timebase is U303, an ovenized 10
MHz crystal oscillator with 5x10-10/day aging and
2x10
-9
stability over 0 to 50 C. This oscillator also
provides a sine wave output which is selected by
the jumper, SW301. When the optional oscillator is
used, U301 reg15 VDC to +12 VDC.
The selected timebase is ac coupled into, and
buffered by, the emitter follower, Q306, which is
coupled to the rear panel output via the 10 MHz
tank, C324 and L305. This output provides a clean
10 MHz, 1 Vrms sinewave, into a 50 Ohm load.
The emitter follower Q307 buffers the 10 MHz sine
wave into U304, an ECL differential line receiver
configured as a Schmitt trigger.
The harmonic generator, U314B, creates a train of
pulses which are 5 ns wide with a pulse repetition
rate of 10 MHz. This pulse train has a frequency
spectrum which has equal amplitude components
at 10,20,30,..to about 100 MHz. The matching
network, L307 and C328, resonates at 90 MHz to
selectively couple the 90 MHz component into the
emitter of the cascode amplifier Q309. The tuned
collector load of Q309 (L306 and C326) provides
the input to the four pole crystal filter.
The crystal filter provides about 80 dB of
selectivity for the 90 MHz signal, which is
discriminated by U305, a fast ECL comparator.
The output of this comparator is the timebase for
all time interval measurements. U312 buffers the
90 MHz clock to reduce crosstalk between various
portions of the instrument. The inductors in each
tank circuit, L307,306,303 and L304 are tuned to
maximize the amplitude of the 90 MHz signal at
TP#1.
The 10 MHz square wave is converted to TTL
levels by U309A to serve as the timebase for the
internal gate generator.
The internal 10 MHz crystal oscillator (either U301
or optional U303) may be phase locked to an
external 5 or 10 MHz reference. The external
reference is ac coupled and buffered by Q308 to
the Schmitt trigger U313A. U313B,C limit the
output to ECL levels, and drive one input to the
ECL phase comparator, U315, an MC12040.
The control line "Ext_5MHz" is high to lock to an
external 5 MHz reference. When high, U314A will
divide by two, providing 5 MHz to the other input of
the phase comparator, U315. To lock to an
external 10 MHz reference, "Ext_5MHz" is low,
and U314A will behave like a one-shot, providing a
10 MHz pulse train to the phase comparator. The
output of the phase comparator is filtered by the -6
dB/octave differential active filter (U316 and
associated R's and C's).
The filtered output of the phase comparator is
used to control the frequency of the crystal
oscillator when -Int_Clk is high. Otherwise, a dc
voltage, V_Freq, sets the oscillator frequency.
(V_Freq may be adjusted in the CAL portion of the
configuration menu.) If the filtered output goes
above +5 Vdc or below -5 Vdc, then the
comparator bit "-Bad_Clk" will go low and the
processor will light the "Clock" LED on the front
panel.
FRONT END INPUTS
(Sheet 8 of 16)
The front-end circuitry is used to discriminate the
A,B and EXT inputs into ECL levels. The inputs
may be ac or dc coupled (except for the EXT input
which is always dc coupled), terminated into 1 M
or 50 Ohms, and compared to levels from -5 to +5
Vdc with 10 mV resolution. Input overloads are
detected (to protect the 50 Ohm terminators) and
a UHF prescaler allows frequency measurements
to 1.3 GHz.
Содержание SR620
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Страница 6: ...iv Table of Contents SR620 Universal Time Interval Counter...
Страница 8: ...vi Safety and Preparation for Use SR620 Universal Time Interval Counter...
Страница 12: ...x Specifications SR620 Universal Time Interval Counter...
Страница 58: ...42 Programming Commands SR620 Universal Time Interval Counter...
Страница 72: ...56 Programming Examples SR620 Universal Time Interval Counter...
Страница 76: ...60 Troubleshooting Tips SR620 Universal Time Interval Counter...
Страница 82: ...66 Performance Test SR620 Universal Time Interval Counter...
Страница 90: ...74 Calibration Procedure SR620 Universal Time Interval Counter...
Страница 102: ...86 Circuit Description SR620 Universal Time Interval Counter...
Страница 124: ...108 Parts List SR620 Universal Time Interval Counter...