Stanford Research Systems SR620, Руководство пользователя

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76 Circuit Description
SR620 Universal Time Interval Counter
GPIB & RS232 commands support these
functions.
RS-232 INTERFACE
(Sheet 2 of 16)
The Z8800 UART output is buffered by 1/4 of
U126 to send data from the instrument to a host
computer. The RS-232 received data is buffered
by 3/4 of U125 and sent to the Z8800 UART input.
The Z8800 can set the bit -RS232CTS low to tell
the host computer that is okay to send data. The
RS232 bits DSR and CD are always high. The
signal from the host computer, DTR (Data
Terminal Ready ), may be used to stop RS232
data output if DTR goes low.
The SR620 is a DCE and may be connected to
PC's using a standard serial cable (not a "null
modem" cable).
SCOPE DISPLAY
(Sheet 3 of 16)
Rear panel outputs provide voltages to display
histograms and graphs on an XY oscilloscope.
The xy coordinates are stored in a list in the 8Kx8
static RAM, U117. This RAM may be written to or
read from by the Z8800. Access to the RAM is had
by asserting the -Busrq bit, at which time the Z80H
(U116) releases the data, address, and control
lines to the RAM, and sets -Busak low, allowing
the Z8800's address, data, and control line to
access the RAM via U114-116.
The Z80, which is clocked at 8 MHz by the crystal
oscillator X102, is executing a short program
(which is also stored in the RAM) which writes xy
pairs to the two 8 bit D/A's. The program can
refresh 3000 points 60 times a second. This
hardware configuration relies on the fortunate fact
that the Z80 instruction, Out(C),A , places the
contents of the C register on the lower eight bits of
the address bus, and the contents of the B register
on the top eight bits of the address bus. This
allows the Z80 to write 16 bits of data
simultaneously to the two D/A converters.
The Z80 executes a halt instruction after
refreshing the XY display. The halt is ended by a
Line_Cross interrupt which starts the next refresh
cycle. A wavering display is avoided by
synchronizing the refresh to the line frequency.
The quad op-amp, U121, provides -10.24 and +5.0
Vdc references to the two DAC's, and converts
their current outputs to voltages. Whenever the
Z80 is halted or has relinquished its bus to the
Z8800, the beam is pulled off the screen by
current injected via D127.
COUNTER INPUT PORTS
(Sheet 4 of 16)
U201 through U203 are used to read data into the
processor. Read instructions which reference the
"data memory" will generate a port strobe to place
data on the processor's data bus.
The seven LSB's from the Tick counter are read
by U201. This counter is called the Tick counter
because it usually counts the clock cycles of the
90 MHz timebase. It may also be used to count
events when in the COUNT Mode.
The seven LSB's from the CYCLE counter are
read by U202. This counter is called the CYCLE
counter because it usually counts the number of
cycles of an input when the unit is in the
FREQUENCY, PERIOD or PHASE Modes.
Key presses may be detected as part of the LED
display refresh. A key press will connect a strobe
line to one of the four input bits, Kbrd_(0-3), which
may be read at the input port U203. If there are no
key presses, all of the Kbrd lines will be low.
The of input bits to U203 are:
Print_Err Detects
printer error
Neg_Time Indicates a Stop before Start
-DTR Low if RS232 device is ready
Cal_En Jumper high to enable calibration
DISPLAY CONTROL OUTPUT PORTS
(Sheet 4 of 16)
U204 though U208 are octal latches (74HCT374)
which latch the data bus contents on the rising
edge of the port strobe. Latched bits perform a
variety of control functions within the instrument
and are used to control the front panel LED
displays and lamps, as well as provide strobes to
read key press data.
U204 selects two digits and ten LED's for refresh.
Only one of the eight bits is strobed low at a time,
saturating one of the transistors in U210 or U211.
Should the port strobe to U204 become inactive,
the one-shot (2/2 U131) will disable the output
drivers so that no LEDs will be damaged. U206
and U207's outputs are set low to turn on
particular segments in the even and odd digits. A