Stanford Research Systems SR620, Руководство пользователя

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Circuit Description 77
SR620 Universal Time Interval Counter
high bit from U208 will saturate a transistor in
U209, lighting the corresponding lamp on the front
panel.
The front panel displays and keyboard are
interface to the main PCB via a 40-pin cable,
J201. Each digit is refreshed for 2 mS. Because
there are large current transients associated with
the multiplexed displays, a se5 supply and
ground return are provided for the LED's.
FRONT-END STATUS BITS
(Sheet 5 of 16)
U233 allows the processor to read various status
bits from the front-end inputs. These status bits
are defined as follows:
Bit Name Function
0 -Bad_Clk
Cold oven or bad Ext timebase
1 -Ovld_A Overload to A's 50 Ohm
terminator
2 -Ovld_B Overload to B's 50 Ohm
terminator
3 -Ovld_Ext Overload to Ext 50 Ohm
terminator
4 -Armed Ready to make a measurement
5 Cmp_3ttl Flag for Ext Trig LED
6 Trig_2 Flag for B's Trig LED
7 Trig_1 Flag for A's Trig LED
The last four bits in the above table are latched by
U231 and U232. Three of the bits are converted
from ECL to TTL levels by U230. All of the flags
may be set with very short pulses ( 3 ns ) and the
flags are cleared after reading when Flagclr is
strobed by the processor.
FRONT-END CONTROL BITS
(Sheet 5 of 16)
U234, and the associated emitter followers Q210-
212 and U239, are used to control front-end
relays. These relays select signal sources for the
comparators, select ac or dc coupling, and control
the 50 Ohm terminators. The definitions of these
control bits is given in the table here:
Bit Name
Function
0 -A_50
Low for 50 Ohm on A
1 -B_50 Low for 50 Ohm on B
2 -Ext_50 Low for 50 Ohm on Ext
3 -A_dc Low for dc couple on A
4 -B_dc Low for dc couple on B
5 CMP1_A/-B Selects A or B for Comp1
6 CMP2_B/-A Selects B or A for Comp2
7 CMP3_E/-C Selects Ext or Int_Cal for
Comp3
ADC, DAC, and MISC CONTROL BITS
(Sheet 5 of 16)
U235 controls the analog-to-digital converter
(ADC) multiplexer, and digital volt meter (DVM)
source and gain. ( See sheet 12 of 16.) The table
below defines each bit:
Bit Name Function
0 Adc_Mpx0
LSB of ADC multiplexer
1 Adc_Mpx1 Middle bit of ADC multiplexer
2 Adc_Mpx2 MSB of ADC multiplexer
3 -Adc_S/H Low to sample DVM input
4 -Adc_Gain Low for 2 VFS, high for 20 VFS
5 Adc1 High to select DVM1
6 -Adc1 Low to select DVM1
7 Int_Gaten High for internal gate enable
There are eight digitally controlled analog voltages
used in the instrument. These voltages are
supplied by one 12 bit digital-to-analog converter
(DAC) which refreshes eight sample-and-hold
amplifiers. ( See sheet 12 of 16.) U236 controls
the DAC multiplexer and provides four other
miscellaneous bits. The definitions for these bits is
given in the table below:
Bit Name Function
0 Dac_Mpx0
DAC multiplexer LSB
1 Dac_Mpx1 DAC multiplexer middle bit
2 Dac_Mpx2 DAC multiplexer MSB
3 Dac_Inh High to inhibit multiplexer
4 Sel_Cmp3 High to start delay on EXT rise
5 -Int_Clk Low to use internal timebase
6 Ttl/-Ecl High for TTL REF output
7 Sel_-Cmp3 High to start delay on EXT fall
There are 24 emitter coupled logic (ECL) level
status bits available from three HC shift registers,
U237, U238 and U250. The outputs from these
ICs swing between -0.7 vdc and -5.2 vdc. Data
from the processor's MSB is shifted serially into
these registers by "Eclshf", and transferred to their
outputs by the port strobe "Rck". The data, clock,
and load bits are level shifted by the resistor
networks N213 and N214. The -0.7 Vdc supply for
the shift registers comes from a transistor in U239.
These ECL level bits allow the processor to control
the mode of the ECL circuits which do the fast
measurements. U237 and the LSB of U238 control