ST10R272L - SYSTEM RESET
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The configuration via P0H is latched only during hardware reset in register RP0H for
subsequent evaluation by software. Register RP0H is described in chapter “The External
Bus Interface”.
Note
The reserved pins (marked “R”) must remain high during reset in order to ensure
proper operation of the ST10R272L. The load on those pins must be small enough
for the internal pullup device to keep their level high, or external pullup devices must
ensure the high level.
The pins marked “X” should be left open for ST10R272L devices that do not use
them.
The following sections describe the different reset configuration options. The default modes
refer to pins at high level, i.e. without external pulldown devices connected. The above note
on reserved pins remains applicable.
15.10.2 Emulation mode
When low during reset, Pin P0L.0 (EMU) selects emulation mode. This mode accesses the
integrated XBUS peripherals by the external bus interface pins in application specific
versions of the ST10R272L.
This mode is used for special emulator purposes and is of no use in basic ST10R272L
devices, so in this case P0L.0 should be held high.
Figure 115 PORT0 configuration during reset
R
R
R
EMU
ADP
R
WRCFG
L.5
L.4
L.3
L.2
L.1
L.0
H.3
H.2 H.
H.0
L.7
L.6
H.7 H.6 H.5
H.4
CSSEL
SALSEL
BUSTYP
RP0H
System Clock
Logic
Port 4
Logic
Port 6
Logic
SYSCON
BUSCON0
Internal Control Logic
(Only on hardware reset)
CLKSEL
(Loaded only on hardware reset)
