ST10R272L - CENTRAL PROCESSING UNIT
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is able to prevent the CPU malfunctioning for long periods of time. After reset, the Watchdog
Timer starts counting automatically, but it can be disabled via software.
Beside its normal operation, there are the following CPU states:
•
Reset: Any reset (hardware, software, watchdog) forces the CPU into a predefined
active state.
•
Idle: The clock signal to the CPU itself is switched off but the clocks for the on-chip
peripherals keep running.
•
Power Down: All of the on-chip clocks are switched off.
A transition into an active CPU state is forced by an interrupt (if being IDLE) or by a reset (if
being in POWER DOWN mode). The IDLE, POWER DOWN and RESET states can be
entered by the use of ST10R272L system control instructions.
4.1
Instruction pipelining
The instruction pipeline partitions instruction processing into four stages:
Fetch:
The instruction selected by the Instruction Pointer (IP), and the Code
Segment Pointer (CSP) is fetched from either the internal RAM or
external memory.
Decode:
The instructions are decoded and, if required, the operand addresses
are calculated and respective operands are fetched. For all
instructions which implicitly access the system stack, the SP register
is either decremented or incremented. For branch instructions, the
Instruction Pointer and the Code Segment Pointer are updated with
the desired branch target address (provided that the branch is taken).
Execute:
An operation is performed on the previously fetched operands in the
ALU. Additionally, the condition flags in the PSW register are updated
as specified by the instruction. All explicit writes to the SFR memory
space and all auto-increment or auto-decrement writes to GPRs used
as indirect address pointers are performed during the execute stage of
an instruction.
Write back:
All external operands and the remaining operands in the internal RAM
space are written back.
4.1.1
Sequential instruction processing
Each single instruction has to pass through each of the four pipeline stages, regardless of
whether all possible stage operations are really performed or not. Since passing through one
pipeline stage takes at least one machine cycle, any isolated instruction takes at least four
machine cycles to be completed. Pipelining allows simultaneous processing of up to four
