ST10R272L - INTERRUPT AND TRAP FUNCTIONS
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When instructions N, N+1 and N+2 are executed out of external memory and the
interrupt vector also points to an external location, but all operands for instructions N-3
through N are in internal memory, then the interrupt response time is the time to perform
3 word bus-accesses.
After an interrupt service routine has been terminated by executing the RETI instruction, and
if further interrupts are pending, the next interrupt service routine will not be entered until at
least two instruction cycles have been executed in the program that was interrupted. In most
cases two instructions will be executed during this time. Typically, only one instruction will be
executed if the first instruction following the RETI instruction is a branch instruction (without
cache hit), or if it is executed out of the internal RAM.
Note
A bus access in this context also includes delays caused by an external READY
signal or by bus arbitration (HOLD mode).
6.7
PEC response times
The PEC response time is the time between the setting of the interrupt request flag of an
enabled interrupt source - to - the start of the PEC data transfer. This is 2 instruction cycles
for the ST10R272L.
The PEC response pipeline has 4 cycles:
Cycle 1:
The interrupt request flag is set (fetching of instruction N).
Cycle 2:
A source wins the prioritization round.
Cycle 3:
A PEC transfer “instruction” is injected into the decode stage of the
pipeline, suspending instruction N+1 and clearing the source's
interrupt request flag to '0'.
Cycle 4:
The injected PEC transfer is completed and execution of instruction
N+1 is resumed.
All instructions that enter the pipeline after the interrupt request flag (N+1, N+2) is set, are
executed after the PEC data transfer.
Note
When instruction N reads any of the PEC control registers PECC7...PECC0 a PEC
request wins the current round of prioritization, this round is repeated and the PEC
data transfer is started one cycle later.
The minimum PEC response time is 3 CPU clock cycles. This requires: program execution
with the fastest bus configuration (16-bit, demultiplexed, no wait states) - no external
operand read requests - setting the interrupt request flag during the last CPU clock cycle of
an instruction.
