ST10R272L - CENTRAL PROCESSING UNIT
40/320
4.1.3
Jump cache instruction processing
A jump cache optimizes conditional jumps that are processed repeatedly in a loop.
Whenever a jump on cache is taken, the extra time to fetch the branch target instruction can
be saved and the corresponding cache jump instruction - in most cases - takes only one
machine cycle.
This performance is achieved by the following mechanism:
Whenever a jump cache instruction passes through the decode stage of the pipeline for the
first time (and provided that the jump condition is met), the jump target instruction is fetched
as usual, causing a time delay of one machine cycle. However, in contrast to standard
branch instructions, the target instruction of a jump cache instruction (JMPA, JMPR, JB,
JBC, JNB, JNBS) is also stored in the cache.
For subsequent execution of the same jump cache instruction, the jump target instruction is
not fetched from program memory, but is taken from the cache and immediately injected into
the decode stage of the pipeline (see figure below).
A jump on cache is always taken after the second and any further occurrence of the same
cache jump instruction, unless:
•
it changes the CSP register contents (JMPS, CALLS, RETS, TRAP, RETI),
•
or a standard interrupt has been processed between two occurrences of the same
cache jump instruction.
Figure 10 Standard branch instruction pipelining
1 Machine
Cycle
FETCH
I
n+2
BRANCH
I
n
. . .
I
TARGET
(I
INJECT
)
BRANCH
I
n
I
1
I
TARGET
(I
INJECT
)
BRANCH
I
3
I
2
I
1
I
TARGET
I
2
I
1
I
TARGET
(I
INJECT
)
BRANCH
I
n
. . .
. . .
DECODE
EXECUTE
WRITEBACK
time
Injection
