ST10R272L - EXTERNAL BUS INTERFACE
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External bus cycles in multiplexed bus modes implicitly add one tri-state time waitstate in
addition to the programmable MTTC waitstate.
9.3.4
Read/write delay time
The timing of the read and write commands can be adjusted to take account of the timing
requirements of external peripherals. The read/write delay controls the time between the
falling edge of ALE and the falling edge of the command. Without read/write delay the falling
edges of ALE and command(s) are coincident (except for propagation delays). With the
delay enabled, the command(s) become active half a CPU clock after the falling edge of
ALE.
The read/write delay does not extend the memory cycle time, and does not slow down the
controller in general. In multiplexed bus modes, however, the data drivers of an external
device may conflict with the ST10R272L’s address, when the early RD signal is used.
Therefore multiplexed bus cycles should always be programmed with read/write delay.
Figure 58 Memory tri-state time
