ST10R272L - ARCHITECTURAL OVERVIEW
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2.3.4
Oscillator watchdog (OWD)
The Oscillator Watchdog provides a fail safe mechanism for the loss of the external clock, for
direct drive or direct drive with prescaler clock options. The oscillator watchdog is enabled by
default after reset. To disable the OWD, set bit OWDDIS of the SYSCON register. When the
OWD is enabled, the PLL runs on its free-running frequency, and increments the Oscillator
Watchdog counter. On each transition of XTAL1 pin, the Oscillator Watchdog is cleared.
If an external clock failure occurs, then the Oscillator Watchdog counter overflows (after 16
PLL clock cycles). The CPU clock signal is switched to the PLL clock signal (the PLL will
runs on its basic frequency of 2...5 MHz), and an Oscillator Watchdog interrupt request
(XP3INT) is flagged. The CPU clock will not switch back to the external clock, even if a valid
external clock exists on the XTAL1 pin. Only a hardware reset can switch the CPU clock
source back to external clock input.
When the OWD is disabled, the CPU clock is always fed from the oscillator input and the PLL
is switched off to decrease power supply current.
2.4
On-chip peripheral blocks
The ST10 family separates its peripherals from the core, allowing peripherals to be added or
removed without modifications to the core. Each functional-block processes data
independently and communicates information over common buses. Peripherals are
controlled by data, written to the Special Function Registers (SFRs). The SFRs are located
in the standard SFR area or the extended ESFR area.
ST10R272L peripherals are:
•
Two general purpose timer blocks (GPT1 and GPT2).
•
One serial interface (ASC0).
•
Watchdog Timer.
•
Seven I/O ports with up to 77 I/O lines.
•
Integrated application-specific synchronous serial port (X-peripheral number 0).
Each peripheral contains a set of Special Function Registers (SFRs) which control the
functionality of the peripheral and temporarily store intermediate data. Each peripheral has
an associated set of status flags. Individually selected clock signals are generated for each
peripheral from binary multiples of the CPU clock.
2.4.1 Peripheral
interfaces
The on-chip peripherals, generally have two different types of interfaces - an interface to the
CPU - and an interface to external hardware. Communication between the CPU and
peripherals is performed through the Special Function Registers (SFRs) and interrupts. The
SFRs serve as control/status and data registers for the peripherals. Interrupt requests are
