ST10R272L - GENERAL PURPOSE TIMER UNITS
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resolution
r
T6
are scaled linearly with lower clock frequencies
f
CPU
, as can be seen from the
following formula:.
The timer resolutions which result from the selected pre-scaler option are listed in the table
below. This table also applies to the Gated Timer Mode of T6 and to the auxiliary timer T5 in
timer and gated timer mode.
Refer to the device datasheet for a table of timer input frequencies, resolution and periods for
the range of pre-scaler options.
Figure 84 Block diagram of core timer T6 in timer mode
Timer Input Selection T5I / T6I
000
B
001
B
010
B
011
B
100
B
101
B
110
B
111
B
Pre-scaler factor
4
8
16
32
64
128
256
512
Resolution in
CPU clock cycles
4
8
16
32
64
128
256
512
Table 38 GPT2 timer resolutions
f
T6
f
C PU
4
2
T6I
〈
〉
×
⁄
=
r
T6
µ
S
[
]
4
2
T6I
〈
〉
×
(
)
f
CPU
⁄
MHz
[
]
=
T6EUD = P5.10
T6OUT = P3.1
x = 6
