ST10R272L - ARCHITECTURAL OVERVIEW
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2.3.1 PLL
operation
The PLL is enabled except when P0H.[7..5] = ‘011’ or ‘001’ during reset. On power-up, the
PLL provides a stable clock-signal within ca. 1 ms after V
CC
has reached 5V+10%, even if
there is no external clock-signal (in this case, the PLL will run at its basic frequency of 2...5
MHz). The PLL will start synchronizing with the external clock signal as soon as it is
available, but only during a hardware reset. The PLL is synchronous with this clock at a
frequency of F * f
XTAL
, i.e. the PLL locks to the external clock.
Note
If the ST10R272L is required to operate on the desired CPU clock directly after
reset, make sure that RSTIN remains active until the PLL has locked (ca. 1 ms).
The PLL constantly synchronizes to the external clock signal. Due to the fact that the
external frequency is 1/F’th of the PLL output frequency, the output frequency may be
slightly higher or lower than the desired frequency. This jitter is irrelevant for long time
periods. For short periods (1...4 CPU clock cycles), it remains below 4%.
When the PLL detects that it is no longer locked, i.e. no longer stable, it generates an
interrupt request (on PLL Unlock XP3INT interrupt node). This occurs when the input clock is
unstable and especially when the input clock fails completely, e.g. due to a broken crystal. In
this case, the synchronization mechanism reduces the PLL output frequency down to the
PLL’s basic frequency (2...5 MHz). The basic frequency is still generated and the CPU can
execute emergency actions.
2.3.2 Prescaler
operation
When pins P0H.[7..5] = ’001’ during reset, the CPU clock is derived from the internal
oscillator (input clock signal) by a 2:1 prescaler.
The frequency of f
CPU
is half the frequency of f
XTAL
.
The PLL runs on a basic frequency of 2...5 MHz, and delivers the clock signal for the
oscillator watchdog.
2.3.3
Direct drive
When pins P0H.[7..5] = ’011’ during reset, the CPU clock is directly driven from the internal
oscillator with the input clock signal, i.e. f
CPU
= f
OSC
. The maximum input clock frequency
depends on the clock signal’s duty cycle, because the minimum values for the clock phases
(TCLs) must be reselected.
The PLL runs on its basic frequency of 2...5 MHz, and delivers the clock signal for the
oscillator watchdog.
1.
The maximum depends on the duty cycle of the external clock signal. The maximum input
frequency is 25 MHz when using an external crystal oscillator, however, higher frequencies
can be applied with an external clock source.
