ST10R272L - INTERRUPT AND TRAP FUNCTIONS
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6.1.3
Interrupt system registers
Interrupt processing is controlled globally by the PSW register through the general interrupt
enable bit (IEN) and the CPU priority field (ILVL). Additionally, the different interrupt sources
are controlled individually by their specific interrupt control registers (...IC). Therefore, the
CPU accepts requests based on the individual interrupt control registers and the PSW. PEC
services are controlled by the respective PECCx register and the source and destination
pointers which specify the PEC service channel task.
6.1.4
Interrupt control registers
All interrupt control registers are organized identically.
•
The lower 8 bits contain the source interrupt status information; this is required during
one round of prioritization,
•
The upper 8 bits are reserved.
•
They are bit addressable and all bits can be read or written to by software - interrupt
sources can be programmed or modified with one instruction.
When accessing interrupt control registers through instructions which operate on word
data-types, their upper 8 bits (15...8) return zeros and discard written data.
The layout of the interrupt control registers shown below applies to each xxIC register, where
xx stands for the source mnemonic.
