A N 9 3
56
Rev. 1.4
Figure 22. Special Trace Layout Technique
23
The trace from C3 to the D1/D2 node should be short and direct.
24
Provide a minimum of 5 mm creepage (or use the capacitor terminal plating spacing
as a guideline for small form factor applications) from any TNV component, pad or
trace, to any SELV component, pad or trace.
25
Minimize the area of the loop formed from U2 pin 4 to R9 to U2 pin 15.
26
Cathode marking for Z1.
27
Pin 1 marking for U1 and U2.
28
Space and mounting holes to accommodate for fire enclosure if necessary.
29
IGND does not extend under C3, D1, FB1, FB2, R15, R16, C8, C9, or RV1.
30
Size Q1, Q3, Q4, and Q5 collector pads to safely dissipate 0.5 W (see text).
31
Submit layout to Silicon Laboratories for review.
Table 43. Layout Checklist (Continued)
P
#
Layout Items
Required
Содержание Si2404
Страница 2: ...AN93 2 Rev 1 4 ...
Страница 27: ...AN93 Rev 1 4 27 Figure 7 Parallel Interface Read Timing Figure 8 Parallel Interface Write Timing ...
Страница 200: ...AN93 200 Rev 1 4 Figure 31 TAM Handset and Speakerphone Voice Paths ...
Страница 201: ...AN93 Rev 1 4 201 Figure 32 Si3000 Codec Gain and Signal Selection Options ...
Страница 290: ...AN93 290 Rev 1 4 Figure 57 256 Band Spectral Display Figure 58 2048 Band Spectral Display ...
Страница 305: ...AN93 Rev 1 4 305 Figure 76 Parallel or SPI Port Interrupt Service Flowchart ...