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304 Rev. 1.4
Interrupt Service Routine (ISR) Method
Transmitting and receiving data to and from the modem is accomplished by servicing the interrupts generated by
the modem. The interrupt sources are described below. Whenever new communication is initiated after a period of
idling with respect to the TXE interrupt, the interrupt must be "jump-started" by calling the interrupt service routine
manually.
RXF Interrupt: Receive FIFO Almost Full
The RXF bit indicates the status of the receive FIFO. If this bit is set, the FIFO is either full (contains 12 bytes) or
almost full (contains 9, 10, or 11 bytes). There are two ways to clear this interrupt: the RXF bit in HIR1 can be
cleared by the host, or enough bytes can be read from the receive FIFO to leave 8 bytes or less, thus removing the
condition for the interrupt. If the host clears the RXF bit, the interrupt is disabled. The interrupt can be rearmed only
when the receive FIFO drops below the ten-byte threshold. The interrupt can then trigger again when the receive
FIFO fills up to ten bytes or more.
TXE Interrupt: Transmit FIFO Almost Empty
This interrupt occurs when only two bytes or fewer remain in the modem's transmit FIFO. The interrupt can be
cleared by writing more data to the FIFO to clear the interrupt condition, or by clearing the TXE bit in the HIR1.
However, if the FIFO is emptied by the modem faster than it is being filled, the TXE interrupt will either persist or
trigger again. If the TXE bit is cleared, the interrupt is disabled and can be rearmed only when three bytes have
been placed into the transmit FIFO. The TXE interrupt may then trigger again when the transmit FIFO drops below
the three-byte threshold. If the transmit FIFO is empty and new data need to be transmitted after the TXE interrupt
has been cleared, the TXE interrupt needs to be jump-started by calling the interrupt service routine manually.
Timer Interrupt: Receive FIFO Not Empty
This interrupt occurs whenever some data remained in the modem's receive FIFO without the FIFO being read for
a period of time set in register U6F. This happens typically at the end of a data burst, when there aren't enough
bytes in the receive FIFO to cause an RXF interrupt, and no more data are received. A timer interrupt can also
occur when the receive FIFO is full if the RXF interrupt was disabled by clearing the RXF bit. The timer is also reset
when new received data are added to the receive FIFO.
The reset value of U6F is 1 ms. The timer interrupt can only be cleared by reading at least one byte from the
receive FIFO. If there remain bytes in the receive FIFO after servicing a timer interrupt, the timer will trigger another
interrupt after the same amount of time specified in the U6F register.
U70 Interrupt
This interrupt is analogous to the interrupt pin when operating in UART mode. It is the result of a condition set in
the U70 register being met, e.g. a parallel phone detection if bit PPDM was set in U70.
The U70 interrupt, indicated by the INT bit in HIR1, can be enabled and disabled using the INTM bit in the same
register. The only way to clear this interrupt is by sending the AT:I command to the modem. Typically, this requires
the application layer to send an ESC control word to place the modem in command mode before sending AT:I. The
response from the AT:I reports the cause of the interrupt. Refer the programmer's guide for more information.
Figure 76 shows the ISR implementation for modem-originated interrupts. The interrupt service routine keeps
running in a loop until all interrupt conditions are cleared.