A N 9 3
34
Rev. 1.4
2.7. EEPROM Interface (24-Pin TSSOP and 38-Pin QFN Only)
The 24-pin TSSOP and 38-pin QFN packages feature an optional three-wire interface (EESD, EECS and EECLK)
that may be directly connected to SPI EEPROMs. An EEPROM may contain custom default settings, firmware
upgrades, and/or user-defined AT command macros for use in custom AT commands or country codes. Firmware
upgrades may also be automatically loaded into the ISOmodem using the BOOT format.
2.7.1. Supported EEPROM Types
The EEPROM must support SPI mode 3 with a 16-bit (8–64 kbit range) address. The EEPROM must be between
8192 and 65536 bits in size and support the commands given in Table 35. The EEPROM must also support 16-bit
addressing regardless of size, allow a clock frequency of at least 1 MHz, assert its output on falling edges of
EECLK and latch input data on rising edges of EECLK. All data are sent to and from the EEPROM with the LSB
first. Required EEPROM command format and signal timing are shown in Tables 35 to 37. A typical EEPROM-
access timing diagram is shown on Figure 11. Such EEPROMs are available from several different manufacturers,
for example:
Microchip: 25LC080..25LC640
Atmel: AT25080..AT25640
WEL = write enable latch
WIP = write in progress
Table 35. EEPROM Commands
Instruction Name
Instruction Format
Description
READ
0000 0011
Read data from memory at address
WRITE
0000 0010
Write data to memory array beginning at address
WRDI
0000 0100
Clear write enable bit (disable write operation)
RDSR
0000 0101
Read status register
WRSR
0000 0001
Write status register
WREN
0000 0110
Set write enable bit (enable write operations)
Table 36. EEPROM Status Register (Any Other Bits are Unused)
7
6
5
4
3
2
1
0
—
—
—
—
—
—
WEL
WIP
Table 37. EEPROM Timing
Parameter
Symbol
Min.
Typ.
Max.
Unit
EECLK period
ECLK
1.0
—
—
µs
EESD input setup time
EISU
100
—
—
ns
EESD input hold time
EIH
100
—
—
ns
EESD output setup time*
EOSU
500
—
—
ns
EESD output hold time*
EOH
500
—
—
ns
EECS asserted to EECLK positive edge
ECSS
500
—
—
ns
Содержание Si2404
Страница 2: ...AN93 2 Rev 1 4 ...
Страница 27: ...AN93 Rev 1 4 27 Figure 7 Parallel Interface Read Timing Figure 8 Parallel Interface Write Timing ...
Страница 200: ...AN93 200 Rev 1 4 Figure 31 TAM Handset and Speakerphone Voice Paths ...
Страница 201: ...AN93 Rev 1 4 201 Figure 32 Si3000 Codec Gain and Signal Selection Options ...
Страница 290: ...AN93 290 Rev 1 4 Figure 57 256 Band Spectral Display Figure 58 2048 Band Spectral Display ...
Страница 305: ...AN93 Rev 1 4 305 Figure 76 Parallel or SPI Port Interrupt Service Flowchart ...