AN93
Rev. 1.4
113
5.7.14. U53 (Modem Control Register 2)
U53 (MOD2) is a bit-mapped register with all bits, except bit 15, reserved (see Table 72). The AT&H11 command
sets the V.23 1200/75 bps mode. Bit 15 (REV) is used to enable V.23 reversing. This bit is set to 0 (disable
reversing) by default. Setting this bit to 1 enables reversing transmit and receive speeds. Reversing is initiated by
the modem in the “origination mode” (low speed TX and high speed RX). U53 resets to 0x0000 with a power-on or
manual reset.
5.7.15. U54 (Calibration Timing Register)
U54 (CALT) sets the time between off-hook and DAA calibration if timed calibration is enabled with the TCAL bit
(U7D, bit 12). The OHCT bits (15:8) control this timing in 32 ms units.
5.7.16. U62–U66 (DAA Control Registers)
U62 (DAAC1) is a bit-mapped register with only bits 1, 2, and 8 available. All other bits in this register are reserved
and must be set according to Table 74. U62 resets to 0x0804 with a power-on or manual reset.
Bit 1 (DL) = 1 or 0 causes digital loopback to occur beyond the isolation capacitor interface out to and including the
analog hybrid circuit. Setting bit 1 high enables digital loopback across the isolation barrier only. This setting is
used in conjunction with the AT&H and AT&T3 commands. DL must be set low for normal operation.
Bit 2 (FOH) controls when automatic Si3018/10 calibration takes place.
Table 71. Transmit Level Register
Register
Name
Description
Default
U52
XMTL
Transmit level adjust (–1 dB units).
0x0000
Table 72. U53 Bit Map
Bit
Name
Function
15
REV
V.23 Reversing.
0
=
Disable.
1 = Enable.
14:0
Reserved
Read returns zero.
Table 73. U54 Bit Map
Bit
Name
Function
15:8
OHCT
Off-hook to calibration timing in 32 ms units. If enabled with TCAL (U7D bit 12), this value
controls the time between off-hook and DAA calibration.
7:0
Reserved
Must be set to zero.
Table 74. U62 Bit Map
Bit
Name
Function
15:12
Reserved
Must be set to zero.
11
Reserved
Must be set to one.
10
FULL2
0 = DAA FULL2 bit cleared.
1 = DAA FULL2 bit set.
9
Reserved
Must be set to zero.
Содержание Si2404
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Страница 27: ...AN93 Rev 1 4 27 Figure 7 Parallel Interface Read Timing Figure 8 Parallel Interface Write Timing ...
Страница 200: ...AN93 200 Rev 1 4 Figure 31 TAM Handset and Speakerphone Voice Paths ...
Страница 201: ...AN93 Rev 1 4 201 Figure 32 Si3000 Codec Gain and Signal Selection Options ...
Страница 290: ...AN93 290 Rev 1 4 Figure 57 256 Band Spectral Display Figure 58 2048 Band Spectral Display ...
Страница 305: ...AN93 Rev 1 4 305 Figure 76 Parallel or SPI Port Interrupt Service Flowchart ...