A N 9 3
42
Rev. 1.4
3.2. AC Termination
The ISOmodem has four ac termination impedances when used with the Si3018 line-side device, selected by the
ACT bits in Register U63. The four available settings for the Si3018 are listed in Table 40. If an ACT[3:0] setting
other than the four listed in Table 40 is selected, the ac termination is forced to 600
(ACT[3:0] = 0000).
3.3. Ringer Impedance and Threshold
The ring detector in many DAAs is ac coupled to the line with a large 1 µF, 250 V decoupling capacitor. The ring
detector on the ISOmodem is resistively coupled to the line. This produces a high ringer impedance to the line of
approximately 20 M
. This meets the majority of country PTT specifications, including FCC and ETSI ES 203 021.
Several countries, including Poland, South Africa, and Slovenia, require a maximum ringer impedance that can be
met with an internally synthesized impedance by setting the RZ bit (Register 67, bit 1).
Some countries specify different ringer thresholds. The RT bit (Register U67, bit 0) selects between two different
ringer thresholds: 15 V ±10% and 21.5 V ±10%. These two settings satisfy ringer threshold requirements
worldwide. The thresholds are set so that a ring signal is guaranteed to be detected above the maximum and not
detected below the minimum.
3.4. Pulse Dialing and Spark Quenching
Pulse dialing is accomplished by going off- and on-hook at a certain cadence to generate make and break pulses.
The nominal rate is ten pulses per second. Some countries have strict specifications for pulse fidelity that include
make and break times, make resistance, and rise and fall times. In a traditional, solid-state dc holding circuit, there
are many problems in meeting these requirements. The ISOmodem dc holding circuit actively controls the on-hook
and off-hook transients to maintain pulse dialing fidelity.
Spark-quenching requirements in countries such as Italy, the Netherlands, South Africa and Australia deal with the
on-hook transition during pulse dialing. These tests provide an inductive dc feed resulting in a large voltage spike.
This spike is caused by the line inductance and sudden decrease in current through the loop when going on-hook.
The traditional solution to the problem is to put a parallel resistive capacitor (RC) shunt across the hookswitch
relay. However, the capacitor required is bulky (~1 µF, 250 V) and relatively costly. In the ISOmodem, the loop
current can be controlled to achieve three distinct on-hook speeds to pass spark-quenching tests without additional
BOM components. Through settings of two bits in two registers, OHS (Register U67, bit 6) and OHS2 (Register
U62, bit 8), a delay between the time the OH bit is cleared and the time the DAA actually goes on-hook, can be
created, which induces a slow ramp-down of the loop current.
3.5. Line Voltage and Loop Current Sensing
There are two methods for line voltage and loop current sensing. The first method is the legacy mode using
U79 (LVCS) [4:0]. The legacy mode is intended for backward compatibility in applications originally designed for
the previous generation ISOmodem. This mode is used in the intrusion detection algorithm implemented on the
device. The legacy mode is set when LLP (UAD [4] = 1 (default).
The second method of measuring line voltage and loop current takes advantage of the improved resolution
available on the Si3018 and Si3010 DAA chips. U63 (LCS) [15:8] represents the value of off-hook loop current as a
non-polar binary number with 1.1 mA/bit resolution. Accuracy is not guaranteed if the loop current is less than the
minimum required for normal DAA operation. U6C (LVS) [15:8] represents the value of on-hook and off-hook loop
voltage as a signed, two’s complement number with a resolution of 1 V/bit.
Table 40. AC Termination Settings for the Si3018 Line-Side Device
ACT[3:0]
AC Termination
0000
600
0011
220
+ (820
|| 120 nF) and 220
+ (820
|| 115 nF)
0100
370
+ (620
|| 310 nF)
1111
Global complex impedance
Содержание Si2404
Страница 2: ...AN93 2 Rev 1 4 ...
Страница 27: ...AN93 Rev 1 4 27 Figure 7 Parallel Interface Read Timing Figure 8 Parallel Interface Write Timing ...
Страница 200: ...AN93 200 Rev 1 4 Figure 31 TAM Handset and Speakerphone Voice Paths ...
Страница 201: ...AN93 Rev 1 4 201 Figure 32 Si3000 Codec Gain and Signal Selection Options ...
Страница 290: ...AN93 290 Rev 1 4 Figure 57 256 Band Spectral Display Figure 58 2048 Band Spectral Display ...
Страница 305: ...AN93 Rev 1 4 305 Figure 76 Parallel or SPI Port Interrupt Service Flowchart ...