SiFive E2* Core IP Series, Руководство пользователя

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Chapter 7
E2 Core IP FPGA Eval Kit MCS Image
Contents
Figure 7.1 shows a block diagram of the E2 Core IP FPGA Eval Kit.
The evaluation kit includes an evaluation Core IP along with additional peripherals and I/Os to
allow software prototyping.
7.1 Core IP FPGA Eval Kit Memory Map
The FPGA design on the Core IP FPGA Eval Kit has an evaluation version of the SiFive E2
Core IP, as well as peripheral devices which are not included with the Core IP deliverable. These
devices allow you to perform basic I/O to prototype and benchmark some basic applications.
Please refer to the Device Tree file, (.dts) for details of the Memory Map.
7.2 Core IP FPGA Eval Kit Clock and Reset
The Core IP FPGA Eval Kit has a 100MHz input to the FPGA. This is used to derive the Core
IP’s
io coreClock
at 65 MHz, and the
clock
(peripheral clock) at 32.5 MHz. The
io rtcToggle
is
driven at approximately 32 kHz.
The system reset driven by the Reset Button on the evaluation board is combined with the external
debugger’s
SRST n
pin as a full system reset for the Core IP FPGA Eval Kit . This is combined with
the
io ndreset
to drive the
reset
input to the Core IP.
The reset vector is set with Switch 0. Leave the switch in the “Off” position to execute from SPI
Flash.
7.3 Core IP FPGA Eval Kit Pinout
The peripherals perform I/O functionalities and are also used to demonstrate the use of Global
Interrupts. The peripheral devices are connected to hardware on the Arty development board
as described in Table
7.1 . Some inputs are wired directly as Global Interrupts, while others go
through the GPIO peripheral.
In addition, some board I/Os are configured as Local Interrupt sources. The mapping between
hardware on the Core IP FPGA Eval Kit and Local Interrupt sources are provided in Table
7.2
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