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23
Table 7.1:
Core IP FPGA Eval Kit GPIO Offset to Board Pin Number
Peripheral
Peripheral Offset
Connections
Global
Interrupt
Number
UART
UART TX/RX
To USB Serial
1
SWITCH 0
Direct Global
2
SWITCH 1
Interrupts
3
SWITCH 2
4
SWITCH 3
5
Quad SPI
all QSPI
To Quad SPI Flash
6
GPIO
GPIO[0]
LED 0 RED
7
GPIO[1]
LED 0 GREEN
8
GPIO[2]
LED 0 BLUE
9
GPIO[3]
SWITCH 3
10
GPIO[4]
BUTTON 0
11
GPIO[5]
BUTTON 1
12
GPIO[6]
BUTTON 2
13
GPIO[7]
BUTTON 3
14
GPIO[8]
PMOD A[0]
15
GPIO[9]
PMOD A[1]
16
GPIO[10]
PMOD A[2]
17
GPIO[11]
PMOD A[3]
18
GPIO[12]
PMOD A[4]
19
GPIO[13]
PMOD A[5]
20
GPIO[14]
PMOD A[6]
21
GPIO[15]
PMOD A[7]
22
PWM/Counter
PWM CMP[0]
23
PWM CMP[1]
LED 1 RED
24
PWM CMP[2]
LED 1 GREEN
25
PWM CMP[3]
LED 1 BLUE
26
Non Core IP
System Reset
LED[4]
System Indicators
Debugger SRST n
LED[5]
dmactive
LED[6]
internal Reset
LED[7]
Содержание E2* Core IP Series
Страница 1: ...SiFive Core IP FPGA Eval Kit User Guide v3p0 SiFive Inc ...
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Страница 8: ...vi SiFive Core IP FPGA Eval Kit User Guide v3p0 ...
Страница 10: ...2 SiFive Core IP FPGA Eval Kit User Guide v3p0 ...
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Страница 28: ...20 SiFive Core IP FPGA Eval Kit User Guide v3p0 ...
Страница 30: ...22 SiFive Core IP FPGA Eval Kit User Guide v3p0 Figure 7 1 E2 Core IP FPGA Eval Kit Block Diagram ...
Страница 34: ...26 SiFive Core IP FPGA Eval Kit User Guide v3p0 Figure 8 1 E3 S5 Core IP FPGA Eval Kit Block Diagram ...
Страница 38: ...30 SiFive Core IP FPGA Eval Kit User Guide v3p0 Figure 9 1 E7 S7 Core IP FPGA Eval Kit Block Diagram ...
