SiFive E2* Core IP Series, Руководство пользователя

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Chapter 1
Introduction
1.1 About this Document
This document gives necessary information for a user of the SiFive Core IP FPGA Eval Kit. To
learn more about the functionality of your specific Core IP please read the appropriate Core IP
Manual.
This guide will help you download and flash the Core IP FPGA Eval Kit image to an FPGA
development board. It will help you install software tools to allow you to write, upload, and debug
code on the Eval Kit. It also contains information about what is contained in the MCS file for the
Core IP FPGA Eval Kit.
1.2 About this Release
This Eval Kit allows you to prototype and benchmark your target RISC-V software without
modifying, integrating, or synthesizing any Verilog code.
This release is intended for evaluation purposes only.
1.3 Evaluation Version Limitations
Version v19.02 of the Core IP FPGA Eval Kit has the following limitations compared with the fully
functional Core IP:
• DTIM is limited in size to 64kB.
• Peripheral Bus, System Bus, and Front Bus are not exported for additional user connections.
The evaluation can utilize the peripherals included on the FPGA.
• Not all Local and Global interrupts are exported at the top level.
To target a different FPGA platform or perform synthesis or simulation, you may obtain an
Evaluation Version of the Core IP RTL from
sifive.com .
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