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R8C/1A Group, R8C/1B Group 9. Bus
Rev.1.30 Dec 08, 2006 Page 57 of 315
REJ09B0252-0130
9. Bus
The bus cycles differ when accessing ROM/RAM, and when accessing SFR. Table 9.1 lists Bus Cycles by Access
Space of the R8C/1A Group and Table 9.2 lists Bus Cycles by Access Space of the R8C/1B Group.
ROM/RAM and SFR are connected to the CPU by an 8-bit bus. When accessing in word (16-bit) units, these areas are
accessed twice in 8-bit units. Table 9.3 lists Access Units and Bus Operations.
Table 9.3 Access Units and Bus Operations
Table 9.1 Bus Cycles by Access Space of the R8C/1A Group
Access Area Bus Cycle
SFR 2 cycles of CPU clock
ROM/RAM 1 cycle of CPU clock
Table 9.2 Bus Cycles by Access Space of the R8C/1B Group
Access Area Bus Cycle
SFR/data flash 2 cycles of CPU clock
Program ROM/RAM 1 cycle of CPU clock
Area SFR, data flash
Even address
Byte access
ROM (program ROM), RAM
Odd address
Byte access
Even address
Word access
Odd address
Word access
CPU clock
Data
Data
Data
Data
Data Data
Data Data
Data
Even
Even
Odd
Odd
Even+1 Even
Odd+1 Odd
Address
Even+1
Odd+1 Odd
Data
Data
Even
Data
CPU clock
Data
Address
CPU clock
Data
Address
CPU clock
Data
Address
Data
CPU clock
Address
Data
CPU clock
Address
Data
CPU clock
Address
Data
CPU clock
Address
Data