R8C/1A Group, R8C/1B Group
15. Serial Interface
Rev.1.30
Dec 08, 2006
Page 158 of 315
REJ09B0252-0130
15.1
Clock Synchronous Serial I/O Mode
In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock. Table 15.1 lists the
Clock Synchronous Serial I/O Mode Specifications. Table 15.2 lists the Registers Used and Settings in Clock
Synchronous Serial I/O Mode
(1)
.
NOTES:
1. If an external clock is selected, ensure that the external clock is “H” when the CKPOL bit in the
U0C0 register is set to 0 (transmit data output at falling edge and receive data input at rising edge of
transfer clock), and that the external clock is “L” when the CKPOL bit is set to 1 (transmit data output
at rising edge and receive data input at falling edge of transfer clock).
2. If an overrun error occurs, the receive data (b0 to b8) of the U0RB register will be undefined. The IR
bit in the S0RIC register remains unchanged.
Table 15.1
Clock Synchronous Serial I/O Mode Specifications
Item
Specification
Transfer data format
• Transfer data length: 8 bits
Transfer clocks
• CKDIR bit in U0MR register is set to 0 (internal clock): fi/(2(n+1)).
fi = f1, f8, f32 n = value set in U0BRG register: 00h to FFh
• The CKDIR bit is set to 1 (external clock): input from CLK0 pin.
Transmit start conditions
• Before transmission starts, the following requirements must be met.
(1)
- The TE bit in the U0C1 register is set to 1 (transmission enabled).
- The TI bit in the U0C1 register is set to 0 (data in the U0TB register).
Receive start conditions
• Before reception starts, the following requirements must be met.
(1)
- The RE bit in the U0C1 register is set to 1 (reception enabled).
- The TE bit in the U0C1 register is set to 1 (transmission enabled).
- The TI bit in the U0C1 register is set to 0 (data in the U0TB register).
Interrupt request
generation timing
• When transmitting, one of the following conditions can be selected.
- The U0IRS bit is set to 0 (transmit buffer empty):
When transferring data from the U0TB register to UART0 transmit
register (when transmission starts).
- The U0IRS bit is set to 1 (transmission completes):
When completing data transmission from UARTi transmit register.
• When receiving
When data transfer from the UART0 receive register to the U0RB register
(when reception completes).
Error detection
• Overrun error
(2)
This error occurs if the serial interface starts receiving the next data item
before reading the U0RB register and receives the 7th bit of the next data.
Select functions
• CLK polarity selection
Transfer data input/output can be selected to occur synchronously with the
rising or the falling edge of the transfer clock.
• LSB first, MSB first selection
Whether transmitting or receiving data begins with bit 0 or begins with bit 7
can be selected.
• Continuous receive mode selection
Receive is enabled immediately by reading the U0RB register.
