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R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface
Rev.1.30 Dec 08, 2006 Page 199 of 315
REJ09B0252-0130
16.3 I
2
C bus Interface
The I
2
C bus interface is the circuit that performs serial communication based on the data transfer format of the
Philips I
2
C bus.
Table 16.5 lists the I
2
C bus interface Specifications, Figure 16.22 shows a Block Diagram of I
2
C bus interface, and
Figure 16.23 shows the External Circuit Connection Example of Pins SCL and SDA. Figures 16.24 to 16.31 show
the registers associated with the I
2
C bus interface.
* I
2
C bus is a trademark of Koninklijke Philips Electronics N. V.
NOTE:
1. All sources use one interrupt vector for I
2
C bus interface.
Table 16.5 I
2
C bus interface Specifications
Item Specification
Communication formats • I 2
C bus format
- Selectable as master/slave device
- Continuous transmit/receive operation (Because the shift register, transmit
data register, and receive data register are independent.)
- Start/stop conditions are automatically generated in master mode.
- Automatic loading of acknowledge bit during transmission
- Bit synchronization/wait function (In master mode, the state of the SCL
signal is monitored per bit and the timing is synchronized automatically. If
the transfer is not possible yet, the SCL signal goes “L” and the interface
stands by.)
- Support for direct drive of pins SCL and SDA (NMOS open drain output)
• Clock synchronous serial format
- Continuous transmit/receive operation (Because the shift register, transmit
data register, and receive data register are independent.)
I/O pins SCL (I/O): Serial clock I/O pin
SDA (I/O): Serial data I/O pin
Transfer clock • When the MST bit in the ICCR1 register is set to 0.
The external clock (input from the SCL pin)
• When the MST bit in the ICCR1 register is set to 1.
The internal clock selected by bits CKS0 to CKS3 in the ICCR1 register
(output from the SCL pin)
Receive error detection • Overrun error detection (clock synchronous serial format)
Indicates an overrun error during reception. When the last bit of the next data
item is received while the RDRF bit in the ICSR register is set to 1 (data in the
ICDRR register), the AL bit is set to 1.
Interrupt sources
• I
2
C bus format .................................. 6 sources
(1)
Transmit data empty (including when slave address matches), transmit ends,
receive data full (including when slave address matches), arbitration lost,
NACK detection, and stop condition detection.
• Clock synchronous serial format ...... 4 sources
(1)
Transmit data empty, transmit ends, receive data full and overrun error
Select functions
• I
2
C bus format
- Selectable output level for acknowledge signal during reception
• Clock synchronous serial format
- MSB-first or LSB-first selectable as data transfer direction