R8C/1A Group, R8C/1B Group
6. Resets
Rev.1.30
Dec 08, 2006
Page 39 of 315
REJ09B0252-0130
Table 6.2 shows the Pin Functions while RESET Pin Level is “L”, Figure 6.2 shows CPU Register Status after Reset
and Figure 6.3 shows Reset Sequence.
Figure 6.2
CPU Register Status after Reset
Figure 6.3
Reset Sequence
Table 6.2
Pin Functions while RESET Pin Level is “L”
Pin Name
Pin Functions
P1
Input port
P3_3
to P3_5, P3_7
Input port
P4_2, P4_5
to
P4_7
Input port
b19
b0
Interrupt table register(INTB)
Program counter(PC)
User stack pointer(USP)
Interrupt stack pointer(ISP)
Static base register(SB)
Content of addresses 0FFFEh to 0FFFCh
Flag register(FLG)
C
IPL
D
Z
S
B
O
I
U
b15
b0
b15
b0
b15
b0
b8
b7
b15
b0
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Data register(R0)
Data register(R1)
Data register(R2)
Data register(R3)
Address register(A0)
Address register(A1)
Frame base register(FB)
00000h
0000h
0000h
0000h
0000h
CPU clock
×
28 cycles
0FFFCh
0FFFEh
0FFFDh
Content of reset vector
20 cycles or more are needed
(1)
fRING-S
Internal reset
signal
CPU clock
Address
(internal address
signal)
NOTE:
1. Hardware reset
Flash memory activation time
(CPU clock
×
11 cycles)
