R8C/1A Group, R8C/1B Group
16. Clock Synchronous Serial Interface
Rev.1.30
Dec 08, 2006
Page 224 of 315
REJ09B0252-0130
16.3.4.3
Receive Operation
In receive mode, data is latched at the rising edge of the transfer clock. The transfer clock is output when the
MST bit in the ICCR1 register is set to 1 and input when the MST bit is set to 0.
Figure 16.43 shows the Operating Timing in Receive Mode (Clock Synchronous Serial Mode).
The receive procedure and operation in receive mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits CKS0 to CKS3 in the
ICCR1 register and set the MST bit (initial setting).
(2) The output of the receive clock starts when the MST bit is set to 1 while the transfer clock is being
output.
(3) Data is transferred from registers ICDRS to ICDRR and the RDRF bit in the ICSR register is set to 1,
when the receive operation is completed. Since the next byte of data is enabled when the MST bit is set
to 1, the clock is output continuously. Continuous reception is enabled by reading the ICDRR register
every time the RDRF bit is set to 1. An overrun is detected at the rise of the 8th clock cycle while the
RDRF bit is set to 1, and the AL bit in the ICSR register is set to 1. At this time, the last receive data is
retained in the ICDRR register.
(4) When the MST bit is set to 1, set the RCVD bit in the ICCR1 register to 1 (disables the next receive
operation) and read the ICDRR register. The SCL signal is fixed “H” after reception of the following
byte of data is completed.
Figure 16.43
Operating Timing in Receive Mode (Clock Synchronous Serial Mode)
SDA
(input)
SCL
8
7
b7
b1
b0
1
2
ICDRR register
ICDRS register
Processing
by program
1
7
8
1
b6
b7
b0
b6
b0
RDRF bit in
ICSR register
1
0
MST bit in
ICCR1 register
1
0
Data 1
Data 2
(2) Set MST bit to 1
(when transfer clock is output)
(3) Read ICDRR register
2
TRS bit in
ICCR1 register
1
0
Data 2
Data 3
Data 1
(3) Read ICDRR register
