R8C/1A Group, R8C/1B Group
16. Clock Synchronous Serial Interface
Rev.1.30
Dec 08, 2006
Page 198 of 315
REJ09B0252-0130
16.2.8
Notes on Clock Synchronous Serial I/O with Chip Select
Set the IICSEL bit in the PMR register to 0 (select clock synchronous serial I/O with chip select function) to use
the clock synchronous serial I/O with chip select function.
16.2.8.1
Accessing Registers Associated with Clock Synchronous Serial I/O
with Chip Select
After waiting three instructions or more after writing to the registers associated with clock synchronous serial I/
O with chip select (00B8h to 00BFh) or four cycles or more after writing to them, read the registers.
•
An example of waiting three instructions or more
Program example
MOV.B
#00h,00BBh
; Set the SSER register to 00h.
NOP
NOP
NOP
MOV.B
00BBh,R0L
•
An example of waiting four cycles or more
Program example
BCLR
4,00BBh
: Disable transmission
JMP.B
NEXT
NEXT:
BSET
3,00BBh
: Enable reception
16.2.8.2
Selecting SSI Signal Pin
Set the SOOS bit in the SSMR2 register to 0 (CMOS output) in the following settings:
•
SSUMS bit in SSMR2 register = 1 (4-wire bus communication mode)
•
BIDE bit in SSMR2 register = 0 (standard mode)
•
MSS bit in SSCRH register = 0 (operate as slave device)
•
SSISEL bit in PMR register = 1 (use P1_6 pin for SSI01 pin)
Do not use the SSI01 pin with NMOS open drain output for the above settings.
