C - 1
REVISION HISTORY
R8C/1A Group, R8C/1B Group Hardware Manual
Rev.
Date
Description
Page
Summary
0.10
Jun 30, 2005
−
First Edition issued
1.00
Sep 09, 2005
all pages “Under development” deleted
3
Table 1.2 Performance Outline of the R8C/1B Group;
Flash Memory:
(Data area)
→
(Data flash)
(Program area)
→
(Program ROM) revised
4
Figure 1.1 Block Diagram;
“Peripheral Function” added,
“System Clock Generation”
→
“System Clock Generator” revised
5
Table 1.3 Product Information of R8C/1A Group;
“(D)” and “(D): Under development” deleted
6
Table 1.4 Product Information of R8C/1B Group;
“(D)” and “(D): Under development” deleted
ROM capacity: “Program area”
→
“Program ROM”,
“Data area”
→
“Data flash” revised
9
Table 1.5 Pin Description;
Power Supply Input: “VCC/AVCC”
→
“VCC”,
“VSS/AVSS”
→
“VSS” revised
Analog Power Supply Input: added
11
Figure 2.1 CPU Register;
“Reserved Area”
→
“Reserved Bit” revised
13
2.8.10 Reserved Area;
“Reserved Area”
→
“Reserved Bit” revised
15
3.2 R8C/1B Group, Figure 3.2 Memory Map of R8C/1B Group;
“Data area”
→
“Data flash”,
“Program area”
→
“Program ROM” revised
17
Table 4.2 SFR Information(2);
004Fh: SSU/IIC Interrupt Control Register
(2)
SSUAIC/IIC2AIC
XXXXX000b added
NOTE2 added
18
Table 4.3 SFR Information(3);
0085h:
“Prescaler Z”
→
“Prescaler Z Register”
0086h:
“Timer Z Secondary”
→
“Timer Z Secondary Register”
0087h:
“Timer Z Primary”
→
“Timer Z Primary Register”
008Ch:
“Prescaler X”
→
“Prescaler X Register”
008Dh:
“Timer X”
→
“Timer X Register”
0090h, 0091h: “Timer C”
→
“Timer C Register” revised
20 to 39 “5. Reset”
→
“5. Programmable I/O Ports” and
“6. Programmable I/O Ports”
→
“6. Reset” revised
31
Table 5.13 Port P3_4/SCS/SDA/CMP1_1 Setting
“SCS”
→
“SCS”
Table 5.14 Port P3_5/SSCK/SCL/CMP1_2 Setting
“SSK”
→
“SSCK”
R8C/1A Group, R8C/1B Group Hardware Manual
REVISION HISTORY
