R8C/1A Group, R8C/1B Group
6. Resets
Rev.1.30
Dec 08, 2006
Page 42 of 315
REJ09B0252-0130
6.2
Power-On Reset Function
When the RESET pin is connected to the VCC pin via a pull-up resistor of about 5 k
Ω,
and the VCC pin voltage
level rises, the power-on reset function is enabled and the MCU resets its pins, CPU, and SFR. When a capacitor is
connected to the RESET pin, always keep the voltage to the RESET pin 0.8VCC or more.
When the input voltage to the VCC pin reaches the Vdet1 level or above, the low-speed on-chip oscillator clock
starts counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held “H”
and the MCU enters the reset sequence (refer to Figure 6.3). The low-speed on-chip oscillator clock divide by 8 is
automatically selected as the CPU after reset.
Refer to
4. Special Function Registers (SFRs)
for the status of the SFR after power-on reset.
The voltage monitor 1 reset is enabled after power-on reset.
Figure 6.6 shows an Example of Power-On Reset Circuit and Operation.
Figure 6.6
Example of Power-On Reset Circuit and Operation
NOTES:
1. The supply voltage must be held within the MCU’s operating voltage range (Vccmin or above) over the sampling time.
2. A sampling clock can be selected. Refer to
7. Voltage Detection Circuit
for details.
3. Vdet1 indicates voltage detection level for the voltage detection 1 circuit. Refer to
7. Voltage Detection Circuit
for details.
4. Refer to
19. Electrical Characteristics.
V
det1
(3)
V
por1
Internal reset signal
(active “L”)
t
w(por1)
t
w(Vpor1–Vdet1)
Sampling time
(1, 2)
V
det1
(3)
1
f
RING-S
×
32
1
f
RING-S
×
32
V
por2
Vccmin
t
w(por2)
t
w(Vpor2–Vdet1)
RESET
VCC
About
5 k
Ω
VCC
RESET
0.1 V to 2.7 V
0 V
0.8 VCC or above
within td(P-R)
0 V
