A - 11
PMCi Function Select Register 2 (PMCiCON2) (i = 0, 1) .................................................411
PMCi Function Select Register 3 (PMCiCON3) (i = 0, 1) ................................................ 413
PMCi Status Register (PMCiSTS) (i = 0, 1) ..................................................................... 414
PMCi Interrupt Source Register (PMCiINT) (i = 0, 1) ...................................................... 417
PMCi Header Pattern Set Register (MIN) (PMCiHDPMIN) (i = 0, 1)
PMCi Header Pattern Set Register (MAX) (PMCiHDPMAX) (i = 0, 1) ............................. 418
PMCi Data 0 Pattern Set Register (MIN) (PMCiD0PMIN) (i = 0, 1)
PMCi Data 0 Pattern Set Register (MAX) (PMCiD0PMAX) (i = 0, 1)
PMCi Data 1 Pattern Set Register (MIN) (PMCiD1PMIN) (i = 0, 1)
PMCi Data 1 Pattern Set Register (MAX) (PMCiD1PMAX) (i = 0, 1) .............................. 420
PMCi Measurements Register (PMCiTIM) (i = 0, 1) ........................................................ 421
PMC0 Receive Bit Count Register (PMC0RBIT) ............................................................. 421
PMC0 Receive Data Store Register i (PMC0DATi) (i = 0 to 5) ........................................ 422
PMC0 Compare Control Register (PMC0CPC) ............................................................... 423
PMC0 Compare Data Register (PMC0CPD) ................................................................... 424
Common Operations in Multiple Modes .......................................................................... 425
Pattern Match Mode (PMC0 and PMC1 Operate Independently) ................................... 427
Pattern Match Mode (Combined Operation of PMC0 and PMC1) ................................... 433
Input Capture Mode (Operating PMC0 and PMC1 Independently) ................................. 438
Input Capture Mode (Simultaneous Count Operation of PMC0 and PMC1) ................... 442
22.5.1
Starting/Stopping PMCi .................................................................................................... 448
22.5.2
Reading the Register ....................................................................................................... 448
22.5.3
Rewriting the Register ..................................................................................................... 448
22.5.4
Combined Operation ....................................................................................................... 449
Peripheral Clock Select Register (PCLKR) ..................................................................... 457
UARTi Transmit/Receive Mode Register (UiMR) (i = 0 to 2, 5 to 7) ................................ 458
UARTi Bit Rate Register (UiBRG) (i = 0 to 2, 5 to 7) ....................................................... 459
UARTi Transmit Buffer Register (UiTB) (i = 0 to 2, 5 to 7) ............................................... 459
UARTi Transmit/Receive Control Register 0 (UiC0) (i = 0 to 2, 5 to 7) ............................ 460
UARTi Transmit/Receive Control Register 1 (UiC1) (i = 0 to 2, 5 to 7) ............................ 462
UARTi Receive Buffer Register (UiRB) (i = 0 to 2, 5 to 7) ............................................... 463
UART Transmit/Receive Control Register 2 (UCON) ...................................................... 465
UARTi Special Mode Register 4 (UiSMR4) (i = 0 to 2, 5 to 7) ......................................... 466
UARTi Special Mode Register 3 (UiSMR3) (i = 0 to 2, 5 to 7) ......................................... 468
UARTi Special Mode Register 2 (UiSMR2) (i = 0 to 2, 5 to 7) ......................................... 469
UARTi Special Mode Register (UiSMR) (i = 0 to 2, 5 to 7) .............................................. 470
Содержание M16C Series
Страница 846: ...M16C 64C Group R01UH0092EJ0110...