R01UH0092EJ0110 Rev.1.10
Page 470 of 807
Jul 31, 2012
M16C/64C Group
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.2.12 UARTi Special Mode Register (UiSMR) (i = 0 to 2, 5 to 7)
BBS (Bus busy flag) (b2)
The BBS bit is set to 0 by a program. (It remains unchanged even if 1 is written.)
ABSCS (Bus collision detect sampling clock select bit) (b4)
When the ABSCS bit is 1, the combinations of UARTi and timer Aj are as follows:
UART0, UART6: Underflow signal of timer A3
UART1, UART7: Underflow signal of timer A4
UART2, UART5: Underflow signal of timer A0
SSS (Transmit start condition select bit) (b6)
When a transmission starts, the SSS bit becomes 0 (not synchronized to RXDi).
Function
Bit Symbol
Bit Name
RW
BBS
ABC
IICM
ACSE
Set to 0
Reserved bit
I
2
C mode select bit
—
(b3)
0 : No auto clear function
1 : Auto clear at bus collision
Auto clear function select bit
of transmit enable bit
RW
RW
RW
RW
RW
Bus busy flag
0 : Stop-condition detected
1 : Start-condition detected (busy)
0 : Other than I
2
C mode
1 : I
2
C mode
Arbitration lost detect flag
control bit
0 : Update every bit
1 : Update every byte
SSS
Transmit start condition
select bit
0 : Not synchronized to RXDi
1 : Synchronized to RXDi
RW
—
(b7)
No register bit. If necessary, set to 0. The read value is undefined.
—
ABSCS
0 : Rising edge of transmit/receive clock
1 : Underflow signal of timer Aj
Bus collision detect sampling
clock select bit
RW
b7
0
b6 b5 b4
b1
b2
b3
b0
UARTi Special Mode Register (i = 0 to 2, 5 to 7)
Symbol
Address
Reset Value
U0SMR, U1SMR, U2SMR
0247h, 0257h, 0267h
X000 0000b
U5SMR, U6SMR, U7SMR
0287h, 0297h, 02A7h
X000 0000b
Содержание M16C Series
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