R01UH0092EJ0110 Rev.1.10
Page 469 of 807
Jul 31, 2012
M16C/64C Group
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.2.11 UARTi Special Mode Register 2 (UiSMR2) (i = 0 to 2, 5 to 7)
Function
Bit Symbol
Bit Name
RW
SWC
CSC
IICM2
SWC2
When arbitration lost is detected,
0 : Do not stop the SDAi output
1 : Stop the SDAi output
SDA output auto stop bit
I
2
C mode select bit 2
ALS
0: Output the transmit/receive clock at the
SCLi pin
1: Hold the SCLi pin low
SCL wait output bit 2
RW
RW
RW
RW
RW
SCL wait auto insert bit
0 : No wait-state/wait-state cleared
1 : Hold the SCLi pin low after the eighth bit
is received
0 : Use NACK/ACK interrupt
1 : Use transmit/receive interrupt
Clock synchronization bit
0 : Clock synchronization disabled
1 : Clock synchronization enabled
SDHI
SDA output disable bit
0: Output data
1: Stop the output (high-impedance)
RW
—
(b7)
No register bit. If necessary, set to 0. The read value is undefined.
—
STAC
When the start condition is detected,
0 : Do not initialize the circuit
1 : Initialize the circuit
UARTi auto initialize bit
RW
b7 b6 b5 b4
b1
b2
b3
b0
Symbol
Address
Reset Value
U0SMR2, U1SMR2, U2SMR2
0246h, 0256h, 0266h
X000 0000b
U5SMR2, U6SMR2, U7SMR2
0286h, 0296h, 02A6h
X000 0000b
UARTi Special Mode Register 2 (i = 0 to 2, 5 to 7)
Содержание M16C Series
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