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Section 2 CPU
Rev. 4.00 Sep. 14, 2005 Page 36 of 982
REJ09B0023-0400
When data is read into the upper 16 bits of a register (bits 31 to 16), the lower 16 bits of the
register (bits 15 to 0) are automatically cleared. A0 and A1 can be stored in the X or Y memory by
this operation, but no other registers can be stored.
The third kind of operation is a single-data transfer instruction, "MOVS.W" or "MOVS.L". These
instructions access any memory location through the LDB (figure 2.8). All DSP registers connect
to the LDB and can be the source or destination register of the data transfer. These instructions
have word and longword access modes. In word mode, registers to be loaded or stored by this
instruction comprise the upper 16 bits (bits 31 to 16) for DSP registers except A0G and A1G.
When data is loaded into a register other than A0G and A1G in word mode, the lower half of the
register is cleared. When A0 or A1 is used, the data is sign-extended to bits 39 to 32 and the lower
half is cleared. When A0G or A1G is the destination register in word mode, data is loaded into an
8-bit register, but A0 or A1 is not cleared. In longword mode, when the destination register is A0
or A1, it is sign-extended to bits 39 to 32.
Tables 2.2 and 2.3 show the data type of registers used in DSP instructions. Some instructions
cannot use some registers shown in the tables because of instruction code limitations. For
example, PMULS can use A1 as the source register, but cannot use A0. These tables ignore details
of register selectability.
Содержание HD6417641
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Страница 11: ...Rev 4 00 Sep 14 2005 Page xi of l USB Universal serial bus WDT Watch dog timer...
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Страница 204: ...Section 4 Clock Pulse Generator CPG Rev 4 00 Sep 14 2005 Page 154 of 982 REJ09B0023 0400...
Страница 212: ...Section 5 Watchdog Timer WDT Rev 4 00 Sep 14 2005 Page 162 of 982 REJ09B0023 0400...
Страница 228: ...Section 6 Power Down Modes Rev 4 00 Sep 14 2005 Page 178 of 982 REJ09B0023 0400...
Страница 246: ...Section 8 X Y Memory Rev 4 00 Sep 14 2005 Page 196 of 982 REJ09B0023 0400...
Страница 318: ...Section 11 User Break Controller UBC Rev 4 00 Sep 14 2005 Page 268 of 982 REJ09B0023 0400...
Страница 454: ...Section 12 Bus State Controller BSC Rev 4 00 Sep 14 2005 Page 404 of 982 REJ09B0023 0400...
Страница 500: ...Section 13 Direct Memory Access Controller DMAC Rev 4 00 Sep 14 2005 Page 450 of 982 REJ09B0023 0400...
Страница 504: ...Section 14 U Memory Rev 4 00 Sep 14 2005 Page 454 of 982 REJ09B0023 0400...
Страница 566: ...Section 17 Compare Match Timer CMT Rev 4 00 Sep 14 2005 Page 516 of 982 REJ09B0023 0400...
Страница 734: ...Section 18 Multi Function Timer Pulse Unit MTU Rev 4 00 Sep 14 2005 Page 684 of 982 REJ09B0023 0400...
Страница 868: ...Section 21 A D Converter Rev 4 00 Sep 14 2005 Page 818 of 982 REJ09B0023 0400...
Страница 914: ...Section 23 I O Ports Rev 4 00 Sep 14 2005 Page 864 of 982 REJ09B0023 0400...
Страница 956: ...Section 24 List of Registers Rev 4 00 Sep 14 2005 Page 906 of 982 REJ09B0023 0400...
Страница 1016: ...Section 25 Electrical Characteristics Rev 4 00 Sep 14 2005 Page 966 of 982 REJ09B0023 0400...
Страница 1024: ...Appendix Rev 4 00 Sep 14 2005 Page 974 of 982 REJ09B0023 0400...
Страница 1032: ...Rev 4 00 Sep 14 2005 Page 982 of 982 REJ09B0023 0400 X X Y data addressing 52 X Y memory 193...
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Страница 1036: ...SH7641 Hardware Manual...