Renesas 89HPES24T3G2ZBAL, Руководство пользователя

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IDT Configuration Registers
PES24T3G2 User Manual 8 - 3 February 22, 2012
Notes
0x00E Byte P0_HDR HDR - Header Type Register (0x00E) on page 8-13
0x00F Byte P0_BIST BIST - Built-in Self Test Register (0x00F) on page 8-13
0x010 DWord P0_BAR0 BAR0 - Base Address Register 0 (0x010) on page 8-13
0x014 DWord P0_BAR1 BAR1 - Base Address Register 1 (0x014) on page 8-14
0x018 Byte P0_PBUSN PBUSN - Primary Bus Number Register (0x018) on page 8-14
0x019 Byte P0_SBUSN SBUSN - Secondary Bus Number Register (0x019) on page 8-14
0x01A Byte P0_SUBUSN SUBUSN - Subordinate Bus Number Register (0x01A) on page 8-14
0x01B Byte P0_SLTIMER SLTIMER - Secondary Latency Timer Register (0x01B) on page 8-14
0x01C Byte P0_IOBASE IOBASE - I/O Base Register (0x01C) on page 8-15
0x01D Byte P0_IOLIMIT IOLIMIT - I/O Limit Register (0x01D) on page 8-15
0x01E Word P0_SECSTS SECSTS - Secondary Status Register (0x01E) on page 8-15
0x020 Word P0_MBASE MBASE - Memory Base Register (0x020) on page 8-16
0x022 Word P0_MLIMIT MLIMIT - Memory Limit Register (0x022) on page 8-16
0x024 Word P0_PMBASE PMBASE - Prefetchable Memory Base Register (0x024) on page 8-
16
0x026 Word P0_PMLIMIT PMLIMIT - Prefetchable Memory Limit Register (0x026) on page 8-17
0x028 DWord P0_PMBASEU PMBASEU - Prefetchable Memory Base Upper Register (0x028) on
page 8-17
0x02C DWord P0_PMLIMITU PMLIMITU - Prefetchable Memory Limit Upper Register (0x02C) on
page 8-17
0x030 Word P0_IOBASEU IOBASEU - I/O Base Upper Register (0x030) on page 8-17
0x032 Word P0_IOLIMITU IOLIMITU - I/O Limit Upper Register (0x032) on page 8-18
0x034 Byte P0_CAPPTR CAPPTR - Capabilities Pointer Register (0x034) on page 8-18
0x038 DWord P0_EROMBASE EROMBASE - Expansion ROM Base Address Register (0x038) on
page 8-18
0x03C Byte P0_INTRLINE INTRLINE - Interrupt Line Register (0x03C) on page 8-18
0x03D Byte P0_INTRPIN INTRPIN - Interrupt PIN Register (0x03D) on page 8-19
0x03E Word P0_BCTL BCTL - Bridge Control Register (0x03E) on page 8-19
0x040 DWord P0_PCIECAP PCIECAP - PCI Express Capability (0x040) on page 8-20
0x044 DWord P0_PCIEDCAP PCIEDCAP - PCI Express Device Capabilities (0x044) on page 8-21
0x048 Word P0_PCIEDCTL PCIEDCTL - PCI Express Device Control (0x048) on page 8-22
0x04A Word P0_PCIEDSTS PCIEDSTS - PCI Express Device Status (0x04A) on page 8-23
0x04C DWord P0_PCIELCAP PCIELCAP - PCI Express Link Capabilities (0x04C) on page 8-24
0x050 Word P0_PCIELCTL PCIELCTL - PCI Express Link Control (0x050) on page 8-25
0x052 Word P0_PCIELSTS PCIELSTS - PCI Express Link Status (0x052) on page 8-27
0x064 DWord P0_PCIEDCAP2 PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) on page 8-
32
0x068 Word P0_PCIEDCTL2 PCIEDCTL2 - PCI Express Device Control 2 (0x068) on page 8-33
Cfg.
Offset
Size
Register
Mnemonic
Register Definition
Table 8.2 Upstream Port 0 Configuration Space Registers (Part 2 of 5)