Renesas 89HPES24T3G2ZBAL, Руководство пользователя

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IDT PES24T3G2 Device Overview
PES24T3G2 User Manual 1 - 6 February 22, 2012
Notes
Pin Description
The following tables list the functions of the pins provided on the PES24T3G2. Some of the functions
listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals
ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals
(including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic
one (high) level.
Note: In the PES24T3G2, the two downstream ports are labeled port 2 and port 4.
Signal Type Name/Description
PE0RP[7:0]
PE0RN[7:0] I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0. Port 0 is the upstream port.
PE0TP[7:0]
PE0TN[7:0] O PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 0. Port 0 is the upstream port.
PE2RP[7:0]
PE2RN[7:0] I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pairs for port 2.
PE2TP[7:0]
PE2TN[7:0] O PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 2.
PE4RP[7:0]
PE4RN[7:0] I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pairs for port 4.
PE4TP[7:0]
PE4TN[7:0] O PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 4.
PEREFCLKP
PEREFCLKN I PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
REFCLKM
1
1.
REFCLKM is not available in the 19mm package and frequency is set at 100MHz.
I PCI Express Reference Clock Mode Select. This signal selects the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
This pin should be static and not change following the negation of
PERSTN.
Table 1.3 PCI Express Interface Pins
Signal Type Name/Description
MSMBADDR[4:1]
1
I Master SMBus Address. These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus.
MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas-
ter SMBus.
SSMBADDR[5,3:1]
2
I Slave SMBus Address. These pins determine the SMBus address to
which the slave SMBus interface responds.
SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
Table 1.4 SMBus Interface Pins (Part 1 of 2)